TDC is connected with FPGA thru two interfaces:

• JTAG
• Parallel

JTAG interface

It is used for programming status register and control register of TDC's. To enable JTAG interface it has to be enabled in FPGA register.

./rwv2 w 0 6 1

After this coresponding lines are connected as below(part of VHDL code):

"...    TDC_TMS                        <= ETRAX_DATA_BUS_C(1);
        TDC_TCK                        <= ETRAX_DATA_BUS_C(2);
        TDC_TDI                        <= ETRAX_DATA_BUS_C(3);
        ETRAX_DATA_BUS_C(0)            <= TDC_TDO; ..."<BR>

TDC's are in JTAG chain. * JTAG chain:

If one of the TDC's fail then it is possible by putting some jumpers(J24,25,26) and removing resistors(R113,114,115) to exclude this TDC from the chain.
For programming TDC and changing settings of TRB refer to the page TDCprogrammingViaJam

Parallel interface

This interface is used for downloading the data from the TDC.

-- MarekPalka - 28 Jun 2007

• TDC readout(from hptdc manual):
  

• hptdc_manual_ver2.2.pdf: hptdc manual