The access to the DSP goes always via the FPGA, in particular the boot strap pins are driven by the FPGA, and this is very important.
I suggest a number of registers in the FPGA dealing with the DSP.
The reset register should have 3 stages:
- Pre-reset: RST_IN of the DSP is pulled down, strap pins are not driven. The user/FPGA has to set the correct values for the strap pins
- Reset: RST_IN of the DSP is pulled down, now the correct values for the strap pins are driven.
- After-reset: RST_IN of the DSP is raised, and the state of the strap pins are latched with the raising edge of RST_IN. The strap pins are outputs now and driven by the DSP!
- 29 Jan 2007