Event and bunch reset signals for TDCs come from FPGA to all four TDCs. In V2 those signals are LVDS and FPGA should drive each TDC separately. For the time being only one terminating resistor should be soldered (instead of four) and possibly a capacitor to slow down the reset signal.
19.12.2006: The layout has been corrected and each mentioned above reset sinal is connected point to point. (8 differential signals going out of FPGA)
The distance of 8 mm between the main TRB board and the add-on card was planned. The connector used is 5 mm high (QTE-040-01). The correct symbol for the 8 mm high connector is QTE-040-02. We can leave with the current one, air flow is smaller but fortunately there is no components making the connection impossible. (5 or 8 mm means the distance between boards when connected).
NB7L86MMNG OR gate was assigned to not existing BGA package. This error forced us to stop manufacturing of next 10 boards. Error has been corrected and NB7L86MMNG has QFN-16 package now.
Virtex banks 1, 3, 4 and 10 did not have the reference resistors for digitally controlled impedance circuit. Errors have been corrected.
Pins in FPGA named by Xilinx: CC, GC and LC cannot be used as the LVDS outputs. ADO_LV[61..0] bus has been re-arranged to make it fully bi-directional. Biggest change applied to bank 1 where no pin can be used as LVDS output.
TDCs need to have their clock disabled during programming. Etrax port A, line PA2 should be connected to SI input of the TDC clock driver (CDCLVD110VF). When the line is LOW TDC clock is enabled and the LED is ON.
A 10-kΩ pullup resistor from CLK1 to VDD and a 10-kΩ pulldown resistor from CLK1b to GND should be added for fail-safe biasing of CDCLVD110VF clock driver.