TIPS about DAQ, kernel, etc.
manual about DAQ readout scripts
TRBvIIHowTo for trb v2
- Quantum Mechanic very well
- prepare boards in Krakow to work done
- prepare script, which open xterms and log on into trb done
- simple unpacker for trb in Cracow done
- prepare 'init daq' applications done radek@depc187:/home/radek/devboard-work_2.4/DAQ
- compile EPICS on trb done EtraxEPICSHowTo
- EPICS -> prepare some testings application done radek@depc187:/home/radek/devboard-work_2.4/apps/epics/base-184.108.40.206/src/makeBaseApp/bin/linux-cris I still have no idea, how can I use casexample & caMonitor
- prepare environment for Coimbra, done
- prepare environment for axis FS, done Tips
- prepare environment for axis FS - onlyRAM version, done see: Second version od dev_system -> only RAM
- loading the kernel into the dev-board, done
- compile the
jam program for etrax_fs done HowToDoIt
- write a device driver which cooperate with IOP DeviceDriver_IOP,
- debugging of crashes and 'enter', It was hardware problem with patches
jam which uses internal register decrease time of programming FPGA from 3min to 7sec
- DMA on IOP, started
- Readout without DMA,
- communication protocol for TRBv2, done
- rwv2 is ready, done
- Reading Serial-Number from Tempsens1 and adapting the startupscripts of the Etrax-FS environment to set the MAC-address corresponding a table Serial Number -> MAC-Address, started
- compile the
jam, which uses coprocessor,
- hwtrb version, which remove TDCheader & TDCtrailer(some kind of compression)
- make jam programming faster,
- use standard HADES-parameter scheme (tcl variables), easiest way would be to use the allParam-library and use external perl-scripts for generating the jam-files
- prepare script, which put parameters, such as search window to trb
- perl compilation
- workshop for students,
* first priority I would set now for you to the standardized control-pograms for the TRB, like trbctrl init trb0 where the settings for trb0 are read from a trb.tcl script, via the param-library and an linked tcl-interpreter. And the same applies for the hwtrb-readout-programm. It is necessary, that it reads for example it's subevent-id from the config-file, as we will have many TRBs, which all need different subevent-id in the datastream.
Main tasks are:
- MDC readout system: implement state machines to write ROC1 and CAL1 (configuration files) into MDC motherboards. Write the TDCs readout code and the transmission protocol to send data to TRBv2.
- TDCs configuration part (ROC1 and CAL1):
- load_ROC1_data_mode.vhd (set the mode lines for the CPLD/TDCs working mode): done
- load_ROC1_tdc_setup.vhd (it loads configuration parameter to one short MB): done
- trigger_begrun_state.vhd: done . It is missing the calibration part.
- trigger_handle_tld.vhd (it synchronize the previous three entities): done
- mode_line_multiplexer.vhd: done
- common_stop_generator.vhd (it generates cms and other control signals for internal use between entities): done
- enable_a_add_data_line_controller.vhd (program to switch a_add line between internal entities) done
- trigger_distributor.vhd (It takes the trigger from the TRB and distribute it to all buses): done .
- PERL script + VHDL program to write/read TDC configuration data into VIRTEX BLOCK of RAM) started
- TDCs calibration part (send calibration parameters to TDCs, get calibration data): done for one short MB, started for chain of MBs.
- mdc_etrax_interface.vhd (Marek's entity. With this entity we are able to write MDC Addon registers through ETRAX): done
- TDC readout:
- send_token_to_mb.vhd(program to send token into TDCs on motherboards: done
- tdc_readout_and_trb_interface.vhd (it reads the data from internal FIFO and send it to the TRB): done .
- program to send/receive data from/to TRBv2: simulated and started implementation in hardware
- my_decode.pl (PERL script to read and decode TDC data): done
- fifo_bus_0.vhd: done .
- Preparation-understanding MDC-DAQ for next beam time: done
- DAQ/FEE tests, FEE exchange, noise test: done
- Full system DAQ test: done
- MDC operation with cosmics: done
- Helmholtz Research School lecture
- IInd semester lecture : done
- Spring lectures weeks : not started
- Summer semester basic lectures-QFT lectures : not started
- 24 Apr 2007: until now I can fix the motherboar's mode lines and I see two tokens back (from MB to Mdc addon), as expected (DSP code). The next step is: add an entity (load_ROC1_tdc_setup.vhd) to the TLD design to load data into TDCs (channel enable, threshold...). Once this is done, I should be able to get data from TDCs every time I send a token with the entity (tdc_readout.vhd). As first approach this data is sended directly to TRBv2.
- 25 Jul 2007: I can load configuration parameters into TDCs and I read them back. I can do this (in token mode) using a special configuration of working mode line (load_ROC1_data_mode.vhd). I can read "real data" from TDCs. This data shows TDC number(4 bits), TDC channel (4 bits), HIT number(1 bit) and data(10 bits). I read back data from one single channel than I enabled 2 channels and so on. Today I enabled all channels of one short motherboard and I read back the data: all channels/TDCs are visible.Today I started to write a more smart programm to read back "real data", to collect data into a FIFO and send this data with header/trailer to TRB. I would send information of possible errors (no token back, event too long....) in the header/trailer words. After that I'll do the same for all 10 buses. So I'll have 10 FIFOs, one for each bus: FIFO_0,...,FIFO_9. I'll collect event in a bigger FIFO and I'll send the event to TRB.
- 04 Mar 2008: I write calibration parameters in to TDCs (CAL1) and I read out the calibration data from 1 short MB. The format of the data is temporary. I cannot get yet "real data" and calibration data at the same time.
- 11 Mar 2008: I get calibration event and normal event together. I start to change dataword format.
- Plans and milestones for next 3 months (04 Mar 2008)
- Calibration (3 days). I should be able to get calibration data and "real" data from TDC.
- Change the dataword format (2 weeks), as agreed with my colleagues.
- Threshold setting (3 weeks): the threshold and all other parameters have to be loaded into Virtex's RAM by ETRAX. At the moment the parameters are hard coded in the VHDL code and they cannot be changed.
- Common stop (3 days). At the moment I generate the common stop internally into the Virtex (on MDC AddOn). Indeed the common stop has to be generated from external electronics.
The previous 3 steps has to be finish at the end of April.
In details: we (Attilio and Joern) agreed (07.03.2008) to have a stable bus readout. For the end of April we should be able to configure one bus (1 short MB, 1 long MB, 2 short MBs, 2 long MBs). I'm not considering the case in which on the same bus there are 3 MB (Dubna plane).
The bus must be configured (ROC1 and CAL1) and the parameters have to be reloaded by ETRAX (not hard-coded). The calibration will be done for all TDCs and all channels (no rotating mask).
- Design generalization (3 weeks): Ones we will have a reliable readout system I will generalize the design to all buses.
- Error handling (3 weeks): I should take care of errors which will happen when we run the full design (10 buses). For example token not back or possibility to disable one bus if it is corrupted..
- MDC AddOn: design optimization (to discuss in a later step).
- MDC End Point: software implementation
- 25 Jul 2007