Difference: CommonStatusRegister (1 vs. 18)

Revision 18
19 Oct 2009 - Main.MichaelBoehmer
Line: 1 to 1
 
META TOPICPARENT name="TrbNetUsersGuide"

Common Status Register

All network devices have one (or more) 32 Bit status registers. These registers will be read out for example once each second using TRBNet. This gives us the possibility to have one computer screen showing the overall status of the detector.
Line: 47 to 47
 

Bits [31:16] of the first register can be used to trigger a board by simple slow control accesses. This is mainly needed for the time where no TRBnet hubs / CTS is available for hardware designers working on the frontend endpoints (nag nag nag). Usage is optional.
Added:
>
>
The LVL1 trigger counter can be set by writing D[15:0] of offset 0x21. Reseting the trigger counter by D8 in offset 0x20 is depreciated! (Jan?)
 

Bit Register 0 (Addr. 0x20) Register 1 (Addr. 0x21)
Changed:
<
<
0 Reset user logic 1 (frontends ?)  
1 Reset user logic 2 (trigger logic ?)  
2 Reset user logic 3  
3 Reset user logic 4  
4    
5    
6    
7    
8 Reset trigger lvl1 counter  
9 Reset trigger lvl2 counter  
10 Reset sequence counter  
11    
12    
13    
14    
15 reboot FPGA from FlashROM  
>
>
0 Reset user logic 1 (frontends ?) trigger_counter_lvl1
1 Reset user logic 2 (trigger logic ?) trigger_counter_lvl1
2 Reset user logic 3 trigger_counter_lvl1
3 Reset user logic 4 trigger_counter_lvl1
4   trigger_counter_lvl1
5   trigger_counter_lvl1
6   trigger_counter_lvl1
7   trigger_counter_lvl1
8   trigger_counter_lvl1
9   trigger_counter_lvl1
10 Reset sequence counter trigger_counter_lvl1
11   trigger_counter_lvl1
12   trigger_counter_lvl1
13   trigger_counter_lvl1
14   trigger_counter_lvl1
15 reboot FPGA from FlashROM trigger_counter_lvl1
 
16 slow control trigger 0  
17 slow control trigger 1  
18 slow control trigger 2  
Revision 17
26 Aug 2009 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetUsersGuide"

Common Status Register

All network devices have one (or more) 32 Bit status registers. These registers will be read out for example once each second using TRBNet. This gives us the possibility to have one computer screen showing the overall status of the detector.
Line: 66 to 66
 
13    
14    
15 reboot FPGA from FlashROM  
Changed:
<
<
16 slow control trigger 0 IPU channel pack bit
>
>
16 slow control trigger 0  
 
17 slow control trigger 1  
18 slow control trigger 2  
19 slow control trigger 3  
Revision 16
26 Aug 2009 - Main.MichaelBoehmer
Line: 1 to 1
 
META TOPICPARENT name="TrbNetUsersGuide"

Common Status Register

All network devices have one (or more) 32 Bit status registers. These registers will be read out for example once each second using TRBNet. This gives us the possibility to have one computer screen showing the overall status of the detector.
Line: 65 to 65
 
12    
13    
14    
Changed:
<
<
15    
>
>
15 reboot FPGA from FlashROM  
 
16 slow control trigger 0 IPU channel pack bit
17 slow control trigger 1  
18 slow control trigger 2  
Revision 15
12 Jun 2009 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetUsersGuide"

Common Status Register

All network devices have one (or more) 32 Bit status registers. These registers will be read out for example once each second using TRBNet. This gives us the possibility to have one computer screen showing the overall status of the detector.
Line: 45 to 45
 

Common Control Register

The first register contains strobe signals: All Bits are automatically cleared one clock cycle after they have been written to one. All other register keeps its data until another write process is done.
Deleted:
<
<
The third register (at address 0x22) contains the global timestamp.
  Bits [31:16] of the first register can be used to trigger a board by simple slow control accesses. This is mainly needed for the time where no TRBnet hubs / CTS is available for hardware designers working on the frontend endpoints (nag nag nag). Usage is optional.
Revision 14
08 Jun 2009 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetUsersGuide"

Common Status Register

All network devices have one (or more) 32 Bit status registers. These registers will be read out for example once each second using TRBNet. This gives us the possibility to have one computer screen showing the overall status of the detector.
Line: 102 to 102
  *also used for unique id
Deleted:
<
<

Board information RAM

There is an 8x16Bit RAM to store information of the board. Since trbnet registers are 32 bit wide, the odd numbered addresses can be accessed as the high word of the register before.

These registers are used for dynamical changeable information about the board that does not need to be accessible via a register.

Register Address RAM Address Content (16Bit)
0x50 0  
  1  
0x51 2  
  3  
0x52 4  
  5  
0x53 6  
  7  

Detailed status register

More detailed information about each electronics board can be obtained by reading out other special registers. Here for example one could see the amount of data sent by each board, the time it needs to deliver data and so on.

Please put a list with the registers needed for your boards
 
Added:
>
>

Detailed register map

The following addresses are currently used on all boards
 
Changed:
<
<
-- JanMichel - 06 Oct 2008
>
>
Address Name Description
0x00 Common Status Register 0 Basic error flags, Temperature
0x01 Common Status Register 1 trigger counter values
0x20 Common Control Register 0 Strobes used for board resets and test triggers
0x21 Common Control Register 1 Common Control signals
0x22 Common Control Register 2 Set global time
0x40 Information ROM 0 Compile time
0x41 Information ROM 1 Design version
0x42 Information ROM 2 Hardware information
0x43 Information ROM 3 ---
0x50 Global Time Read global time
0x51 Time Since Trigger Read time since last timing trigger received
 
Revision 13
03 Jun 2009 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetUsersGuide"

Common Status Register

All network devices have one (or more) 32 Bit status registers. These registers will be read out for example once each second using TRBNet. This gives us the possibility to have one computer screen showing the overall status of the detector.
Line: 62 to 62
 
7    
8 Reset trigger lvl1 counter  
9 Reset trigger lvl2 counter  
Changed:
<
<
10    
>
>
10 Reset sequence counter  
 
11    
12    
13    
Revision 12
29 May 2009 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetUsersGuide"

Common Status Register

All network devices have one (or more) 32 Bit status registers. These registers will be read out for example once each second using TRBNet. This gives us the possibility to have one computer screen showing the overall status of the detector.
Line: 43 to 43
 

Common Control Register

Changed:
<
<
The first register contains strobe signals: All Bits are automatically cleared one clock cycle after they have been written to one. The second register keeps its data until another write process is done. There are no further registers defined up to now.
>
>
The first register contains strobe signals: All Bits are automatically cleared one clock cycle after they have been written to one. All other register keeps its data until another write process is done.

The third register (at address 0x22) contains the global timestamp.

Bits [31:16] of the first register can be used to trigger a board by simple slow control accesses. This is mainly needed for the time where no TRBnet hubs / CTS is available for hardware designers working on the frontend endpoints (nag nag nag). Usage is optional.
 
Deleted:
<
<
Bits [31:16] can be used to trigger a board by simple slow control accesses. This is mainly needed for the time where no TRBnet hubs / CTS is available for hardware designers working on the frontend endpoints (nag nag nag). Usage is optional.
 

Bit Register 0 (Addr. 0x20) Register 1 (Addr. 0x21)
0 Reset user logic 1 (frontends ?)  
Revision 11
29 May 2009 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetUsersGuide"

Common Status Register

All network devices have one (or more) 32 Bit status registers. These registers will be read out for example once each second using TRBNet. This gives us the possibility to have one computer screen showing the overall status of the detector.
Line: 43 to 43
 

Common Control Register

Changed:
<
<
The first register contains strobe signals: All Bits are automatically cleared one clock cycle after they have been written to one. All other registers keep their data until another write process is done THIS SEEMS NOT TO WORK?. There are no further registers defined up to now.
>
>
The first register contains strobe signals: All Bits are automatically cleared one clock cycle after they have been written to one. The second register keeps its data until another write process is done. There are no further registers defined up to now.
 

Bits [31:16] can be used to trigger a board by simple slow control accesses. This is mainly needed for the time where no TRBnet hubs / CTS is available for hardware designers working on the frontend endpoints (nag nag nag). Usage is optional.
Changed:
<
<
Bit Register 1 (Addr. 0x20)
0 Reset user logic 1 (frontends ?)
1 Reset user logic 2 (trigger logic ?)
2 Reset user logic 3
3 Reset user logic 4
4  
5  
6  
7  
8 Reset trigger lvl1 counter
9 Reset trigger lvl2 counter
10  
11  
12  
13  
14  
15 IPU channel pack bit
16 slow control trigger 0
17 slow control trigger 1
18 slow control trigger 2
19 slow control trigger 3
20 slow control trigger 4
21 slow control trigger 5
22 slow control trigger 6
23 slow control trigger 7
24 slow control trigger 8
25 slow control trigger 9
26 slow control trigger 10
27 slow control trigger 11
28 slow control trigger 12
29 slow control trigger 13
30 slow control trigger 14
31 slow control trigger 15
>
>
Bit Register 0 (Addr. 0x20) Register 1 (Addr. 0x21)
0 Reset user logic 1 (frontends ?)  
1 Reset user logic 2 (trigger logic ?)  
2 Reset user logic 3  
3 Reset user logic 4  
4    
5    
6    
7    
8 Reset trigger lvl1 counter  
9 Reset trigger lvl2 counter  
10    
11    
12    
13    
14    
15    
16 slow control trigger 0 IPU channel pack bit
17 slow control trigger 1  
18 slow control trigger 2  
19 slow control trigger 3  
20 slow control trigger 4  
21 slow control trigger 5  
22 slow control trigger 6  
23 slow control trigger 7  
24 slow control trigger 8  
25 slow control trigger 9  
26 slow control trigger 10  
27 slow control trigger 11  
28 slow control trigger 12  
29 slow control trigger 13  
30 slow control trigger 14  
31 slow control trigger 15  
 

Board information ROM

Revision 10
22 May 2009 - Main.MichaelBoehmer
Line: 1 to 1
 
META TOPICPARENT name="TrbNetUsersGuide"

Common Status Register

All network devices have one (or more) 32 Bit status registers. These registers will be read out for example once each second using TRBNet. This gives us the possibility to have one computer screen showing the overall status of the detector.
Line: 43 to 43
 

Common Control Register

Changed:
<
<
The first register contains strobe signals: All Bits are automatically cleared one clock cycle after they have been written to one. All other registers keep their data until another write process is done. There are no further registers defined up to now.
>
>
The first register contains strobe signals: All Bits are automatically cleared one clock cycle after they have been written to one. All other registers keep their data until another write process is done THIS SEEMS NOT TO WORK?. There are no further registers defined up to now.
 
Changed:
<
<
Bits [31:16] can be used to trigger a board by simple slow control accesses. This is mainly needed for the time where no TRBnet hubs ( CTS is available for hardware designers working on the frontend endpoints (nag nag nag). Usage is optional.
>
>
Bits [31:16] can be used to trigger a board by simple slow control accesses. This is mainly needed for the time where no TRBnet hubs / CTS is available for hardware designers working on the frontend endpoints (nag nag nag). Usage is optional.
 

Bit Register 1 (Addr. 0x20)
Changed:
<
<
0 Reset user logic 1
1 Reset user logic 2
>
>
0 Reset user logic 1 (frontends ?)
1 Reset user logic 2 (trigger logic ?)
 
2 Reset user logic 3
3 Reset user logic 4
4  
Line: 63 to 63
 
12  
13  
14  
Changed:
<
<
15  
>
>
15 IPU channel pack bit
 
16 slow control trigger 0
17 slow control trigger 1
18 slow control trigger 2
Revision 9
09 Mar 2009 - Main.MichaelBoehmer
Line: 1 to 1
 
META TOPICPARENT name="TrbNetUsersGuide"

Common Status Register

All network devices have one (or more) 32 Bit status registers. These registers will be read out for example once each second using TRBNet. This gives us the possibility to have one computer screen showing the overall status of the detector.
Line: 43 to 43
 

Common Control Register

Changed:
<
<
The first register contains strobe signals: All Bits are automatically cleared one clock cycle after they have been written to one. All other registers keep their data until another write process is done.
>
>
The first register contains strobe signals: All Bits are automatically cleared one clock cycle after they have been written to one. All other registers keep their data until another write process is done. There are no further registers defined up to now.
 
Changed:
<
<
Bit Register 1 (Addr. 0x20) Register 2 (Addr. 0x21)
0 Reset user logic 1  
1 Reset user logic 2  
2 Reset user logic 3  
3    
4    
5    
6    
7    
8 Reset trigger lvl1 counter  
9 Reset trigger lvl2 counter  
10    
11    
12    
13    
14    
15    
16    
17    
18    
19    
20    
21    
22    
23    
24    
25    
26    
27    
28    
29    
30    
31    
>
>
Bits [31:16] can be used to trigger a board by simple slow control accesses. This is mainly needed for the time where no TRBnet hubs ( CTS is available for hardware designers working on the frontend endpoints (nag nag nag). Usage is optional.

Bit Register 1 (Addr. 0x20)
0 Reset user logic 1
1 Reset user logic 2
2 Reset user logic 3
3 Reset user logic 4
4  
5  
6  
7  
8 Reset trigger lvl1 counter
9 Reset trigger lvl2 counter
10  
11  
12  
13  
14  
15  
16 slow control trigger 0
17 slow control trigger 1
18 slow control trigger 2
19 slow control trigger 3
20 slow control trigger 4
21 slow control trigger 5
22 slow control trigger 6
23 slow control trigger 7
24 slow control trigger 8
25 slow control trigger 9
26 slow control trigger 10
27 slow control trigger 11
28 slow control trigger 12
29 slow control trigger 13
30 slow control trigger 14
31 slow control trigger 15
 

Board information ROM

Revision 8
09 Mar 2009 - Main.MichaelBoehmer
Line: 1 to 1
 
META TOPICPARENT name="TrbNetUsersGuide"

Common Status Register

All network devices have one (or more) 32 Bit status registers. These registers will be read out for example once each second using TRBNet. This gives us the possibility to have one computer screen showing the overall status of the detector.
Line: 6 to 6
  Additionally there are some status bits that are transported with every data transfer - These are merged ("wired-or") for all boards, so these contain some very rough information only. See TrbNetDatafields#Error_bits for details.

Bit Register 1 (Addr. 0x00) Register 2 (Addr. 0x01)
Changed:
<
<
0 serious error* triggger_counter_lvl1
1 error* triggger_counter_lvl1
2 warning* triggger_counter_lvl1
3 info* triggger_counter_lvl1
4 trigger1_counter_mismatch* triggger_counter_lvl1
5 trigger2_counter_mismatch* triggger_counter_lvl1
6   triggger_counter_lvl1
7   triggger_counter_lvl1
8   triggger_counter_lvl1
9   triggger_counter_lvl1
10   triggger_counter_lvl1
11   triggger_counter_lvl1
12   triggger_counter_lvl1
13   triggger_counter_lvl1
14   triggger_counter_lvl1
15   triggger_counter_lvl1
16   triggger_counter_lvl2
17   triggger_counter_lvl2
18   triggger_counter_lvl2
19   triggger_counter_lvl2
20 temperature triggger_counter_lvl2
21 temperature triggger_counter_lvl2
22 temperature triggger_counter_lvl2
23 temperature triggger_counter_lvl2
24 temperature triggger_counter_lvl2
25 temperature triggger_counter_lvl2
26 temperature triggger_counter_lvl2
27 temperature triggger_counter_lvl2
28 temperature triggger_counter_lvl2
29 temperature triggger_counter_lvl2
30 temperature triggger_counter_lvl2
31 temperature triggger_counter_lvl2
>
>
0 serious error* trigger_counter_lvl1
1 error* trigger_counter_lvl1
2 warning* trigger_counter_lvl1
3 info* trigger_counter_lvl1
4 trigger1_counter_mismatch* trigger_counter_lvl1
5 trigger2_counter_mismatch* trigger_counter_lvl1
6   trigger_counter_lvl1
7   trigger_counter_lvl1
8   trigger_counter_lvl1
9   trigger_counter_lvl1
10   trigger_counter_lvl1
11   trigger_counter_lvl1
12   trigger_counter_lvl1
13   trigger_counter_lvl1
14   trigger_counter_lvl1
15   trigger_counter_lvl1
16   trigger_counter_lvl2
17   trigger_counter_lvl2
18   trigger_counter_lvl2
19   trigger_counter_lvl2
20 temperature trigger_counter_lvl2
21 temperature trigger_counter_lvl2
22 temperature trigger_counter_lvl2
23 temperature trigger_counter_lvl2
24 temperature trigger_counter_lvl2
25 temperature trigger_counter_lvl2
26 temperature trigger_counter_lvl2
27 temperature trigger_counter_lvl2
28 temperature trigger_counter_lvl2
29 temperature trigger_counter_lvl2
30 temperature trigger_counter_lvl2
31 temperature trigger_counter_lvl2
  *same as in Errorbits
  • The temperature is starting in the middle of a byte. This is done by purpose, since bits 20 to 23 represent the fractional part of the temperature.
Revision 7
08 Oct 2008 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetUsersGuide"

Common Status Register

All network devices have one (or more) 32 Bit status registers. These registers will be read out for example once each second using TRBNet. This gives us the possibility to have one computer screen showing the overall status of the detector.
Line: 43 to 43
 

Common Control Register

Added:
>
>
The first register contains strobe signals: All Bits are automatically cleared one clock cycle after they have been written to one. All other registers keep their data until another write process is done.
 
Bit Register 1 (Addr. 0x20) Register 2 (Addr. 0x21)
Changed:
<
<
0 Reset user logic  
1    
2    
>
>
0 Reset user logic 1  
1 Reset user logic 2  
2 Reset user logic 3  
 
3    
4    
5    
Line: 79 to 81
 

Board information ROM

Changed:
<
<
There is an 8x16Bit RAM to store information of the board. Since trbnet registers are 32 bit wide, the odd numbered addresses can be accessed as the high word of the register before.
>
>
There is an 8x16Bit RAM to store information of the board. Since trbnet registers are 32 bit wide, the odd numbered addresses are read out as the high word of the register before.
 
Changed:
<
<
Register Address Address Content (16Bit)
>
>
Register Address RAM Address Content (16Bit)
 
0x40 0 Compile time low word
  1 Compile time high word
0x41 2 Compile version
Line: 94 to 96
  *also used for unique id
Added:
>
>

Board information RAM

There is an 8x16Bit RAM to store information of the board. Since trbnet registers are 32 bit wide, the odd numbered addresses can be accessed as the high word of the register before.

These registers are used for dynamical changeable information about the board that does not need to be accessible via a register.

Register Address RAM Address Content (16Bit)
0x50 0  
  1  
0x51 2  
  3  
0x52 4  
  5  
0x53 6  
  7  
 

Detailed status register

More detailed information about each electronics board can be obtained by reading out other special registers. Here for example one could see the amount of data sent by each board, the time it needs to deliver data and so on.
Revision 6
06 Oct 2008 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetUsersGuide"

Common Status Register

All network devices have one (or more) 32 Bit status registers. These registers will be read out for example once each second using TRBNet. This gives us the possibility to have one computer screen showing the overall status of the detector.

Additionally there are some status bits that are transported with every data transfer - These are merged ("wired-or") for all boards, so these contain some very rough information only. See TrbNetDatafields#Error_bits for details.
Changed:
<
<
Please feel free to put additional status information to this table!

Bit Register 1 (Addr. 0) Register 2 (Addr. 1)
>
>
Bit Register 1 (Addr. 0x00) Register 2 (Addr. 0x01)
 
0 serious error* triggger_counter_lvl1
1 error* triggger_counter_lvl1
2 warning* triggger_counter_lvl1
Line: 44 to 42
 
  • The temperature is starting in the middle of a byte. This is done by purpose, since bits 20 to 23 represent the fractional part of the temperature.
Added:
>
>

Common Control Register

Bit Register 1 (Addr. 0x20) Register 2 (Addr. 0x21)
0 Reset user logic  
1    
2    
3    
4    
5    
6    
7    
8 Reset trigger lvl1 counter  
9 Reset trigger lvl2 counter  
10    
11    
12    
13    
14    
15    
16    
17    
18    
19    
20    
21    
22    
23    
24    
25    
26    
27    
28    
29    
30    
31    
 

Board information ROM

Line: 51 to 83
 

Register Address Address Content (16Bit)
Changed:
<
<
x0040 0 Compile time low word
>
>
0x40 0 Compile time low word
 
  1 Compile time high word
Changed:
<
<
x0041 2 Compile version
>
>
0x41 2 Compile version
 
  3  
Changed:
<
<
x0042 4 Hardware info 0
>
>
0x42 4 Hardware info 0
 
  5 Hardware info 1
Changed:
<
<
x0043 6  
>
>
0x43 6  
 
  7  
*also used for unique id
Line: 72 to 104
 

Changed:
<
<
-- JanMichel - 01 Apr 2008
>
>
-- JanMichel - 06 Oct 2008
 
Revision 5
18 Apr 2008 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetUsersGuide"

Common Status Register

All network devices have one (or more) 32 Bit status registers. These registers will be read out for example once each second using TRBNet. This gives us the possibility to have one computer screen showing the overall status of the detector.
Line: 47 to 47
 

Board information ROM

Changed:
<
<
There is an 16x16Bit RAM to store information of the board. Since trbnet registers are 32 bit wide, the odd numbered addresses can be accessed as the high word of the register before.
>
>
There is an 8x16Bit RAM to store information of the board. Since trbnet registers are 32 bit wide, the odd numbered addresses can be accessed as the high word of the register before.
 

Register Address Address Content (16Bit)
Line: 55 to 55
 
  1 Compile time high word
x0041 2 Compile version
  3  
Changed:
<
<
x0042 4 00 & Board_Information_0*
  5 Board_Information_1*
>
>
x0042 4 Hardware info 0
  5 Hardware info 1
 
x0043 6  
  7  
Deleted:
<
<
x0044 8  
  9  
x0045 10  
  11  
x0046 12  
  13  
x0047 14  
  15  
  *also used for unique id
Revision 4
09 Apr 2008 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetUsersGuide"

Common Status Register

All network devices have one (or more) 32 Bit status registers. These registers will be read out for example once each second using TRBNet. This gives us the possibility to have one computer screen showing the overall status of the detector.
Line: 51 to 51
 

Register Address Address Content (16Bit)
Changed:
<
<
128 0 Compile time low word
>
>
x0040 0 Compile time low word
 
  1 Compile time high word
Changed:
<
<
129 2 Compile version
  3 00 & Board_Information_0*
130 4 Board_Information_1*
  5  
131 6  
>
>
x0041 2 Compile version
  3  
x0042 4 00 & Board_Information_0*
  5 Board_Information_1*
x0043 6  
 
  7  
Changed:
<
<
132 8  
>
>
x0044 8  
 
  9  
Changed:
<
<
133 10  
>
>
x0045 10  
 
  11  
Changed:
<
<
134 12  
>
>
x0046 12  
 
  13  
Changed:
<
<
135 14  
>
>
x0047 14  
 
  15  
*also used for unique id
Revision 3
03 Apr 2008 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetUsersGuide"
Deleted:
<
<
 

Common Status Register

All network devices have one (or more) 32 Bit status registers. These registers will be read out for example once each second using TRBNet. This gives us the possibility to have one computer screen showing the overall status of the detector.
Line: 8 to 7
 

Please feel free to put additional status information to this table!
Changed:
<
<
Bit Register 1 Register 2
>
>
Bit Register 1 (Addr. 0) Register 2 (Addr. 1)
 
0 serious error* triggger_counter_lvl1
1 error* triggger_counter_lvl1
2 warning* triggger_counter_lvl1
Line: 29 to 28
 
17   triggger_counter_lvl2
18   triggger_counter_lvl2
19   triggger_counter_lvl2
Changed:
<
<
20   triggger_counter_lvl2
21   triggger_counter_lvl2
22   triggger_counter_lvl2
23   triggger_counter_lvl2
24   triggger_counter_lvl2
25   triggger_counter_lvl2
26   triggger_counter_lvl2
27   triggger_counter_lvl2
28   triggger_counter_lvl2
29   triggger_counter_lvl2
30   triggger_counter_lvl2
31   triggger_counter_lvl2
>
>
20 temperature triggger_counter_lvl2
21 temperature triggger_counter_lvl2
22 temperature triggger_counter_lvl2
23 temperature triggger_counter_lvl2
24 temperature triggger_counter_lvl2
25 temperature triggger_counter_lvl2
26 temperature triggger_counter_lvl2
27 temperature triggger_counter_lvl2
28 temperature triggger_counter_lvl2
29 temperature triggger_counter_lvl2
30 temperature triggger_counter_lvl2
31 temperature triggger_counter_lvl2
  *same as in Errorbits
Added:
>
>
  • The temperature is starting in the middle of a byte. This is done by purpose, since bits 20 to 23 represent the fractional part of the temperature.
 

Board information ROM

Changed:
<
<
There is an 16x16Bit RAM to store information of the board.
>
>
There is an 16x16Bit RAM to store information of the board. Since trbnet registers are 32 bit wide, the odd numbered addresses can be accessed as the high word of the register before.
 
Changed:
<
<
Address Content (16Bit)
0 Compile time low word
1 Compile time high word
2 Compile version
3 00 & Board_Information_0*
4 Board_Information_1*
5  
6  
7  
8  
9  
10  
11  
12  
13  
14  
15  
>
>
Register Address Address Content (16Bit)
128 0 Compile time low word
  1 Compile time high word
129 2 Compile version
  3 00 & Board_Information_0*
130 4 Board_Information_1*
  5  
131 6  
  7  
132 8  
  9  
133 10  
  11  
134 12  
  13  
135 14  
  15  
  *also used for unique id
Revision 2
01 Apr 2008 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetUsersGuide"
Added:
>
>
 

Common Status Register

All network devices have one (or more) 32 Bit status registers. These registers will be read out for example once each second using TRBNet. This gives us the possibility to have one computer screen showing the overall status of the detector.
Line: 8 to 9
  Please feel free to put additional status information to this table!

Bit Register 1 Register 2
Changed:
<
<
0    
1    
2    
3    
4    
5    
6    
7    
8    
9    
10    
11    
12    
13    
14    
15    
16    
17    
18    
19    
20    
21    
22    
23    
24    
25    
26    
27    
28    
29    
30    
31    
>
>
0 serious error* triggger_counter_lvl1
1 error* triggger_counter_lvl1
2 warning* triggger_counter_lvl1
3 info* triggger_counter_lvl1
4 trigger1_counter_mismatch* triggger_counter_lvl1
5 trigger2_counter_mismatch* triggger_counter_lvl1
6   triggger_counter_lvl1
7   triggger_counter_lvl1
8   triggger_counter_lvl1
9   triggger_counter_lvl1
10   triggger_counter_lvl1
11   triggger_counter_lvl1
12   triggger_counter_lvl1
13   triggger_counter_lvl1
14   triggger_counter_lvl1
15   triggger_counter_lvl1
16   triggger_counter_lvl2
17   triggger_counter_lvl2
18   triggger_counter_lvl2
19   triggger_counter_lvl2
20   triggger_counter_lvl2
21   triggger_counter_lvl2
22   triggger_counter_lvl2
23   triggger_counter_lvl2
24   triggger_counter_lvl2
25   triggger_counter_lvl2
26   triggger_counter_lvl2
27   triggger_counter_lvl2
28   triggger_counter_lvl2
29   triggger_counter_lvl2
30   triggger_counter_lvl2
31   triggger_counter_lvl2
*same as in Errorbits

Board information ROM

There is an 16x16Bit RAM to store information of the board.

Address Content (16Bit)
0 Compile time low word
1 Compile time high word
2 Compile version
3 00 & Board_Information_0*
4 Board_Information_1*
5  
6  
7  
8  
9  
10  
11  
12  
13  
14  
15  
*also used for unique id
 

Detailed status register

Line: 52 to 79
 

Changed:
<
<
-- JanMichel - 31 Mar 2008
>
>
-- JanMichel - 01 Apr 2008
 
 
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