Difference: DescriptionOfFPGA (1 vs. 8)

Revision 8
23 Jul 2008 - Main.MarekPalka
Line: 1 to 1
 
META TOPICPARENT name="TRBvIIHowTo"
A VIRTEX4 LX40 FPGA is used on the TRBv2.

FPGA registers

r/w adress bits
Changed:
<
<
r 1 31-lvl2 busy 30-16:reserved 15:lvl1 memory busy 14:lvl1 busy 13-4:how many words in lvl1 buffer 3-0:TDCD,C,B,A error
r 2 31-20:reserved 19-0:how many words in event
r 3 31-0:data from lvl1 fifo
r 4 31-8:reserved 7-4:lvl1 trigger state machine:
x"0":invalid
x"1":IDLE
x"2"-x"5":SEND_LVL1_TRIGG_1-4
x"6":WAIT_FOR_TOKEN
x"7"-x"a":SAVE_ADD_DATA_1-4
3-2:reserved 1-0:lvl delay state machine:
00:invalid
11-IDLE
01:DELAY_1
10:DELAY_2
>
>
r 0 31-26 not used ADO_LV 25-0
r 1 31-lvl2 busy 30:lvl1_fifo_wr_en 29-16: lvl1_fifo_counter 15:lvl1 or lvl2_is_busy 14:lvl1 busy 13-4:how many words in lvl1 buffer 3-0:TDCD,C,B,A error
r 2 31-27:not used 26-24:lvl2_debug:001: IDLE
010: READOUT_WORD1
011: READOUT_WORD2
100: SAVE_EVENT_SIZE
101: SEND_DATA1
23-20:LVL1 state:
x"1": IDLE
x"2"-x"5": SEND_LVL1_TRIGG_1-4
x"6": WAIT_FOR_TOKEN
x"7"-x"a": SAVE_ADD_DATA_1-4
x"c": SEND_LVL2_TRIGG
19-18: delay trigger FSM: 01: IDLE
10: DELAY_1
11: DELAY_2
15-0:how many words in event
r 3 31-0: lvl1_buffer_out
r 4 31-28: not used 27-24: LVL1 CODE 23-16: LVL1 TAG 15-12: not used 11-8:lvl1_code -internal 7-0: lvl1 tag minus 1
 
r 5 31-24:how many lvl2 busy ended 23-16:how many times lvl2 started 15-8:how many times token was received 7-0:how many times lvl1 started
Changed:
<
<
r/w 6 31-24:additional delay time for trigger to TDC's 23-16:how many add data(counters) 15-10:reserved 9:eneble SPI for RPC 8:enable ext. trigger 7:enable self trigger 6:enable tdc clock(trbva) 5:dsp boff(active low) 4:dsp reset(active low) 3:dsp bm and bms 2:enable test signal(2)-1kHz- 1:enable test signal(1)-1kHz 0:enable JTAG for TDC
>
>
r/w 6 31-24:additional delay time for trigger to TDC's 10ns resolution 23-16:how many add data(counters) 15-10:reserved 9:eneble SPI for RPC 8:enable ext. trigger 7:enable self trigger 6:enable tdc clock(trbva) 5:dsp boff(active low) 4:dsp reset(active low) 3:dsp bm and bms 2:enable test signal trigger(2)-100Hz- 1:enable test signal trigger(1)-100Hz 0:enable JTAG for TDC
 
r/w 7 31-12:reserved 11:spi_cs_d 10:spi_sdo_d 9:spi_sck_d 8:spi_cs_c 7:spi_sdo_c 6:spi_sck_c 5:spi_cs_b 4:spi_sdo_b 3:spi_sck_b 2:spi_cs_a 1:spi_sdo_a 0:spi_sck_a
r 8 31-4:reserved 3:spi_sdi_d 2:spi_sdi_c 1:spi_sdi_b 0:spi_sdi_a
Changed:
<
<
>
>
r/w e 31-16:not used 15-8:trb data version 7-4:enable test signal b MB3-0 3-0:enable test signal a MB3-0
 

FPGA interfaces

Etrax

Revision 7
07 Aug 2007 - Main.MarekPalka
Line: 1 to 1
 
META TOPICPARENT name="TRBvIIHowTo"
A VIRTEX4 LX40 FPGA is used on the TRBv2.
Line: 10 to 10
 
r 3 31-0:data from lvl1 fifo
r 4 31-8:reserved 7-4:lvl1 trigger state machine:
x"0":invalid
x"1":IDLE
x"2"-x"5":SEND_LVL1_TRIGG_1-4
x"6":WAIT_FOR_TOKEN
x"7"-x"a":SAVE_ADD_DATA_1-4
3-2:reserved 1-0:lvl delay state machine:
00:invalid
11-IDLE
01:DELAY_1
10:DELAY_2
r 5 31-24:how many lvl2 busy ended 23-16:how many times lvl2 started 15-8:how many times token was received 7-0:how many times lvl1 started
Changed:
<
<
r/w 6 31-24:additional delay time for trigger to TDC's 23-16:how many add data(counters) 15-11:reserved 10:enable test signal - 1kHz 9:eneble SPI for RPC 8:enable ext. trigger 7:enable self trigger 6:enable tdc clock(trbva) 5:dsp boff(active low) 4:dsp reset(active low) 3:dsp bm and bms 2-1:reserved 0:enable JTAG for TDC
>
>
r/w 6 31-24:additional delay time for trigger to TDC's 23-16:how many add data(counters) 15-10:reserved 9:eneble SPI for RPC 8:enable ext. trigger 7:enable self trigger 6:enable tdc clock(trbva) 5:dsp boff(active low) 4:dsp reset(active low) 3:dsp bm and bms 2:enable test signal(2)-1kHz- 1:enable test signal(1)-1kHz 0:enable JTAG for TDC
 
r/w 7 31-12:reserved 11:spi_cs_d 10:spi_sdo_d 9:spi_sck_d 8:spi_cs_c 7:spi_sdo_c 6:spi_sck_c 5:spi_cs_b 4:spi_sdo_b 3:spi_sck_b 2:spi_cs_a 1:spi_sdo_a 0:spi_sck_a
r 8 31-4:reserved 3:spi_sdi_d 2:spi_sdi_c 1:spi_sdi_b 0:spi_sdi_a
Revision 6
06 Aug 2007 - Main.MichaelTraxler
Line: 1 to 1
 
META TOPICPARENT name="TRBvIIHowTo"
Changed:
<
<
On trbv2 platform it is used the VIRTEX4 lx40 FPGA.
>
>
A VIRTEX4 LX40 FPGA is used on the TRBv2.
 

FPGA registers

r/w adress bits
Line: 16 to 17
 

FPGA interfaces

Etrax

Changed:
<
<
Etrax with first strobe is sneding a mode in which it wants to operate(R/W). If it is only read mode then it sending only 32 bit address,if it is write mode it sends also 32 bit data. To read data from FPGA register it is needed to type: ./rwv2 r 0 1 : where rwv2 is read write program, r - mode, 0 - which device(FPGA), 1 - address inside the device.
>
>
The Etrax is sending a mode in which it wants to operate(R/W) with the first strobe. If it is the "read mode" then it sending only 32 bit address,if it is the "write mode" it sends also 32 bit data. To read data from the FPGA registers one has to use the following command: ./rwv2 r 0 1 : where rwv2 is the read write program, r - mode, 0 - which device(FPGA), 1 - address inside the device.
  For writing ./rwv2 w 2 ab 01234567 : where w - mode, 2 -device number(SDRAM), ab- address, 01234567 - value to write
Line: 33 to 34
  * Etrax FS and FPGA protocol:
EtraxFS and FPGA protocol
Changed:
<
<
All devices are connected thru ETRAX-FPGA interface. It can be develop for future needs (add on interface, sfp ...)
>
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All devices are accessible by the ETRAX-FPGA interface. It can be extended for future needs (add on interface, SFP ...)
 

* Connection between interfaces:
Connection between interfaces

DSP

All needed information should be found on: http://www.analog.com/processors/tigersharc/technicalLibrary/manuals/index.html
Changed:
<
<
Now DSP interface is used as host interface between DSP and FPGA. Main signal are HBR - host bus request, HBG - host bus granted, WRL,WRH - write , RD - read, BRST- burst, ACK - acknowledgment. To start reading or writing DSP has to go from reset state:
>
>
Currently, the DSP interface is used as a host interface between DSP and FPGA. The main signals are HBR - host bus request, HBG - host bus grant, WRL,WRH - write , RD - read, BRST- burst, ACK - acknowledge. To start reading or writing the DSP has to leave the reset state:
  ./rwv2 w 0 6 30 Then it is possible to write or read:

./rwv2 r 1 0x1xxxxxxx
Changed:
<
<
For reading and writing offset address is 0x10000000. It is like this because TigerSHARC DSP is working in multi processor system.
>
>
For accessing the Sharc, the offset address is 0x10000000, because the TigerSHARC DSP is a multi processor system (first device).
 

SDRAM

Changed:
<
<
Now it is existing simple entity just for checking if it is possible to write or read to SDRAM
>
>
Now it is existing a simple entity just for checking if it is possible to write or read to SDRAM
  For reading : ./rwv2 r 2 0x110
Line: 64 to 65
 

Optical and SFP

Changed:
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<
This interface will be use for trb net data transmition (2Gbit). There are existing entities which are using this interface. From SFP it i spossible to readout tempreture and optical power.
>
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This interface will be use for trb net data transmition (2Gbit). There are entities available which are using this interface. From the SFP one can read out the temperature and the optical power.
 

Addo-on

Changed:
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For controlling and checking the status of addon board.
>
>
For controlling and checking the status of add-on boards.
 

VULOM

Changed:
<
<
This
>
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To be done.
 

-- MarekPalka - 27 Jun 2007
Revision 5
03 Aug 2007 - Main.MarekPalka
Line: 1 to 1
 
META TOPICPARENT name="TRBvIIHowTo"
On trbv2 platform it is used the VIRTEX4 lx40 FPGA.

FPGA registers

Line: 9 to 9
 
r 3 31-0:data from lvl1 fifo
r 4 31-8:reserved 7-4:lvl1 trigger state machine:
x"0":invalid
x"1":IDLE
x"2"-x"5":SEND_LVL1_TRIGG_1-4
x"6":WAIT_FOR_TOKEN
x"7"-x"a":SAVE_ADD_DATA_1-4
3-2:reserved 1-0:lvl delay state machine:
00:invalid
11-IDLE
01:DELAY_1
10:DELAY_2
r 5 31-24:how many lvl2 busy ended 23-16:how many times lvl2 started 15-8:how many times token was received 7-0:how many times lvl1 started
Changed:
<
<
w 6 31-24:additional delay time for trigger to TDC's 23-16:how many add data(counters) 15-11:reserved 10:enable test signal - 1kHz 9:eneble SPI for RPC 8:enable ext. trigger 7:enable self trigger 6:enable tdc clock(trbva) 5:dsp boff(active low) 4:dsp reset(active low) 3:dsp bm and bms 2-1:reserved 0:enable JTAG for TDC
>
>
r/w 6 31-24:additional delay time for trigger to TDC's 23-16:how many add data(counters) 15-11:reserved 10:enable test signal - 1kHz 9:eneble SPI for RPC 8:enable ext. trigger 7:enable self trigger 6:enable tdc clock(trbva) 5:dsp boff(active low) 4:dsp reset(active low) 3:dsp bm and bms 2-1:reserved 0:enable JTAG for TDC
r/w 7 31-12:reserved 11:spi_cs_d 10:spi_sdo_d 9:spi_sck_d 8:spi_cs_c 7:spi_sdo_c 6:spi_sck_c 5:spi_cs_b 4:spi_sdo_b 3:spi_sck_b 2:spi_cs_a 1:spi_sdo_a 0:spi_sck_a
r 8 31-4:reserved 3:spi_sdi_d 2:spi_sdi_c 1:spi_sdi_b 0:spi_sdi_a
 

FPGA interfaces

Revision 4
03 Aug 2007 - Main.MarekPalka
Line: 1 to 1
 
META TOPICPARENT name="TRBvIIHowTo"
On trbv2 platform it is used the VIRTEX4 lx40 FPGA.

FPGA registers

Changed:
<
<
r/w adress bits
r 1 31-lvl2 busy 30-16:reserved 15:lvl1 memory busy 14:lvl1 busy 13-4:how many words in lvl1 buffer 3-0:TDCD,C,B,A error
r 2 31-20:reserved 19-0:how many words in event
r 3 31-0:data from lvl1 fifo
r 4 31-8:reserved 7-4:lvl1 trigger state machine:
x"0":invalid
x"1":IDLE
x"2"-x"5":SEND_LVL1_TRIGG_1-4
x"6":WAIT_FOR_TOKEN
x"7"-x"a":SAVE_ADD_DATA_1-4
3-2:reserved 1-0:lvl delay state machine:
00:invalid
11-IDLE
01:DELAY_1
10:DELAY_2
r 5 31-24:how many lvl2 busy ended 23-16:how many times lvl2 started 15-8:how many times token was received 7-0:how many times lvl1 started
w 6 31-24:additional delay time for trigger to TDC's 23-16:how many add data(counters) 15-8:reserved 7:enable self trigger 6:enable tdc clock(trbva) 5:dsp boff(active low) 4:dsp reset(active low) 3:dsp bm and bms 2-0:reserved
>
>
r/w adress bits
r 1 31-lvl2 busy 30-16:reserved 15:lvl1 memory busy 14:lvl1 busy 13-4:how many words in lvl1 buffer 3-0:TDCD,C,B,A error
r 2 31-20:reserved 19-0:how many words in event
r 3 31-0:data from lvl1 fifo
r 4 31-8:reserved 7-4:lvl1 trigger state machine:
x"0":invalid
x"1":IDLE
x"2"-x"5":SEND_LVL1_TRIGG_1-4
x"6":WAIT_FOR_TOKEN
x"7"-x"a":SAVE_ADD_DATA_1-4
3-2:reserved 1-0:lvl delay state machine:
00:invalid
11-IDLE
01:DELAY_1
10:DELAY_2
r 5 31-24:how many lvl2 busy ended 23-16:how many times lvl2 started 15-8:how many times token was received 7-0:how many times lvl1 started
w 6 31-24:additional delay time for trigger to TDC's 23-16:how many add data(counters) 15-11:reserved 10:enable test signal - 1kHz 9:eneble SPI for RPC 8:enable ext. trigger 7:enable self trigger 6:enable tdc clock(trbva) 5:dsp boff(active low) 4:dsp reset(active low) 3:dsp bm and bms 2-1:reserved 0:enable JTAG for TDC
 

FPGA interfaces

Revision 3
23 Jul 2007 - Main.MichaelTraxler
Line: 1 to 1
Changed:
<
<
META TOPICPARENT name="HowTo"
>
>
META TOPICPARENT name="TRBvIIHowTo"
  On trbv2 platform it is used the VIRTEX4 lx40 FPGA.

FPGA registers

Revision 2
28 Jun 2007 - Main.MarekPalka
Line: 1 to 1
 
META TOPICPARENT name="HowTo"
Added:
>
>
On trbv2 platform it is used the VIRTEX4 lx40 FPGA.
 

FPGA registers

r/w adress bits
Line: 25 to 26
  2-SDRAM
3-Add on board - not existing
4-SFP - not existing
Changed:
<
<
>
>
...
 

* Etrax FS and FPGA protocol:
EtraxFS and FPGA protocol
Added:
>
>

All devices are connected thru ETRAX-FPGA interface. It can be develop for future needs (add on interface, sfp ...)

* Connection between interfaces:
Connection between interfaces
 

DSP

Added:
>
>
All needed information should be found on: http://www.analog.com/processors/tigersharc/technicalLibrary/manuals/index.html Now DSP interface is used as host interface between DSP and FPGA. Main signal are HBR - host bus request, HBG - host bus granted, WRL,WRH - write , RD - read, BRST- burst, ACK - acknowledgment. To start reading or writing DSP has to go from reset state: ./rwv2 w 0 6 30 Then it is possible to write or read:

./rwv2 r 1 0x1xxxxxxx

For reading and writing offset address is 0x10000000. It is like this because TigerSHARC DSP is working in multi processor system.
 

SDRAM

Added:
>
>

Now it is existing simple entity just for checking if it is possible to write or read to SDRAM For reading : ./rwv2 r 2 0x110

http://download.micron.com/pdf/datasheets/dram/sdram/512MbSDRAM.pdf
 

TDC

Changed:
<
<

Optical

>
>

This interface is for downloading the TDC measurements. * Parallel interface:
Parallel interface

Optical and SFP

This interface will be use for trb net data transmition (2Gbit). There are existing entities which are using this interface. From SFP it i spossible to readout tempreture and optical power.
 

Addo-on

Added:
>
>
For controlling and checking the status of addon board.

VULOM

This
  -- MarekPalka - 27 Jun 2007

Line: 38 to 76
  -- MarekPalka - 27 Jun 2007

Added:
>
>

 
META FILEATTACHMENT attr="" comment="EtraxFS and FPGA protocol" date="1182958230" name="protocol_final.jpg" path="protocol_final.jpg" size="94326" user="MarekPalka" version="1.1"
Added:
>
>
META FILEATTACHMENT attr="" comment="Connection between interfaces" date="1183024584" name="inside_fpga.jpg" path="inside_fpga.jpg" size="95171" user="MarekPalka" version="1.2"
META FILEATTACHMENT attr="" comment="Parallel interface" date="1183035489" name="tdcinterface.jpg" path="tdcinterface.jpg" size="95430" user="MarekPalka" version="1.3"
 
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