Difference: DevBoardPatches (1 vs. 5)

Revision 5
27 Oct 2009 - Main.JanMichel
Line: 1 to 1
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META TOPICPARENT name="TDCReadoutBoard"
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META TOPICPARENT name="TRBBoardErrors"
 

List of patches compiled by Marcin on 06.05.2005

Error list in order of tracing them:
Line: 68 to 68
 

-- MichaelTraxler - 09 Nov 2005
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META TOPICMOVED by="JanMichel" date="1256641044" from="DaqSlowControl.TRBListofDevBoardPatches" to="DaqSlowControl.DevBoardPatches"
Revision 4
17 Jan 2006 - Main.MichaelTraxler
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

List of patches compiled by Marcin on 06.05.2005

Line: 53 to 53
 
  • Trigger Bus should have a switch to turn on or off the termination-resistors.
  • The dual-ported ram should be a FIFO, as there is no need for a DP-RAM and an FIFO is much easier to use.
  • The TriggerBus should have one large connector for all 20 pairs, as there is no need to separate them
Added:
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  • Proposal: Usage of high density cable, VHDCI connectors and cables, standard in IT-technology (SCSI), 8 connectors (68 pins) would fit in one VME-front-panel, for LVL1 and LVL2 at once. Cables can be bought in length upt to 10m (90). Or we can use the same cable and connectors as for the RPC-FEE signals, KEL 40 pins, and standard bus-technology, so IDC cabling.
 
  • Take care that the trigger-timing signal has the correct polarity. On the current board U16 uses switched clock inputs.

Other improvements

  • Using new technology switching power supply: PME5218TS (same kind for all voltages)
Changed:
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  • Shielding of 48V power supply
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  • Shielding of 48V power supply, usage of new 48V DC/DC converter technology from C&D
 
  • take care that the 48V are really galvanically isolated
  • more ground pads for connection to detector
Revision 3
06 Dec 2005 - Main.MichaelTraxler
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

List of patches compiled by Marcin on 06.05.2005

Line: 56 to 56
 
  • Take care that the trigger-timing signal has the correct polarity. On the current board U16 uses switched clock inputs.
Added:
>
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Other improvements

  • Using new technology switching power supply: PME5218TS (same kind for all voltages)
  • Shielding of 48V power supply
  • take care that the 48V are really galvanically isolated
  • more ground pads for connection to detector
 

Revision 2
16 Nov 2005 - Main.MichaelTraxler
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

List of patches compiled by Marcin on 06.05.2005

Line: 12 to 12
 
  1. DC/DC should not be close to TDC
  2. LED D25 on the bottom side
  3. JTL connectors should have keep-out area
Changed:
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  1. Two single switches instead of switch1
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  1. Two single switches instead of switch1, and a connector which allows to contol this state via an external voltage (for example HahShoPoMo)
 
  1. Missing JTAG connector for programming Spartan and TDC via cable
  2. Schmidt trigger BGA chip in between two big capacitors
  3. two different via diameters on the board
Line: 45 to 45
 

Added:
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Bugs found during beam-test Nov2005

  • There is a bug in the schematics: Device U12A, the pin 9A (27) has to be lifted as it otherwise will drive against GND.
  • Busy and Error signal on Trigger-Bus can not be tristated. This prevents us from using a trigger BUS, we can only use point to point connections.
  • Trigger Bus should have a switch to turn on or off the termination-resistors.
  • The dual-ported ram should be a FIFO, as there is no need for a DP-RAM and an FIFO is much easier to use.
  • The TriggerBus should have one large connector for all 20 pairs, as there is no need to separate them
  • Take care that the trigger-timing signal has the correct polarity. On the current board U16 uses switched clock inputs.

  -- MichaelTraxler - 09 Nov 2005
 
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