Difference: EtraxTRBInterface (1 vs. 3)

Revision 3
29 Jun 2012 - Main.JanMichel
Line: 1 to 1
Changed:
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META TOPICPARENT name="TrbNetUsersGuide"
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META TOPICPARENT name="DaqUpgrade"
 

Interface between Etrax and FPGA on TRB ("TrbNet edition")

Revision 2
30 Jan 2009 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetUsersGuide"

Interface between Etrax and FPGA on TRB ("TrbNet edition")

Line: 40 to 40
 
  1. FPGA sets lower 16bit of data and datavalid, Etrax acknowledges with strobe
Changed:
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Proposal: Use only a 16bit address with included read/write-select to access registers on this interface. There is no need to stay compatible with the address width of the DSP which is definitely not used on the CTS. This would save 40% of time for each access.
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>
Proposal: Use only a 16bit address with included read/write-select to access registers on this interface. There is no need to stay compatible with the address width of the DSP which is definitely not used on the CTS. This would save 40% of time for each access. Therefore, the first three steps are merged into a single word where Bit 15 sets the mdoe of operation (1: read, 0: write) and the other bits form a 15bit address.
 

Registers for TrbNet Access

The registers implemented for sending and receiving data over TrbNet are as follows.
 
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