Difference: HowToRunMDCDaq (1 vs. 18)

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META TOPICPARENT name="DaqUpgradeMDCOverview"
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  -- AttilioTarantola - 05 Aug 2008

The software configures and takes data from 10 buses.
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./rw_mdc_addon w 0 0E 0B003D
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-- AttilioTarantola - 01 Oct 2008

Here some data example which the FEE delivers without sending the token:

When the token does not respond within 10mses, and the data is not corrupted, the event looks like this:

Empty event without token back:

Calibration event without token back:

 

Test in the cave

-- AttilioTarantola - 12 Aug 2008
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META FILEATTACHMENT attr="" comment="3 bus normal event" date="1217323113" name="3bus_normal_event.txt" path="3bus_normal_event.txt" size="2254" user="AttilioTarantola" version="1.1"
META FILEATTACHMENT attr="" comment="data from 10 buses" date="1217599425" name="data_10buses.txt" path="data_10buses.txt" size="4167" user="AttilioTarantola" version="1.1"
META FILEATTACHMENT attr="" comment="planeI sector3 data" date="1218555726" name="10_bus_plane1_sector3.txt" path="10_bus_plane1_sector3.txt" size="25156" user="AttilioTarantola" version="1.1"
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META FILEATTACHMENT attr="" comment="data drom 1 bus and NO token back" date="1222852959" name="notok_with_data.txt" path="notok_with_data.txt" size="1744" user="AttilioTarantola" version="1.1"
META FILEATTACHMENT attr="" comment="NO data from 1 bus and NO token back" date="1222853215" name="notok_no_data.txt" path="notok_no_data.txt" size="765" user="AttilioTarantola" version="1.1"
META FILEATTACHMENT attr="" comment="calibration data from 1 bus and NO token back" date="1222853370" name="notok_cal_data.txt" path="notok_cal_data.txt" size="3696" user="AttilioTarantola" version="1.1"
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1. login in the ETRAX as ROOT.
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2. program FPGA on TRB: /home/hadaq/jamv2_reg aRUN_XILINX_PROC /home/hadaq/Mdc_addon/trb_mdc_test7.stapl
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2. program FPGA on TRB: /home/hadaq/jamv2_reg -aRUN_XILINX_PROC /home/hadaq/Mdc_addon/trb_mdc_test7.stapl
 

3. set the environment: export DAQ_SETUP=pion9
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jamv2_reg -aRUN_XILINX_PROC /home/hadaq/mdc_addon/trb_mdc_test7.stapl
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(with external trigger trb_mdc_test8.stapl)
  jamv2_addon-aRUN_XILINX_PROC /home/hadaq/mdc_addon/readout_test_2_clkto_trb_10bus_busn_mux.stapl

rw_mdc_addon w 0 7 931C261 (MB number: fixed)
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Test in the cave

-- AttilioTarantola - 12 Aug 2008

One TRB+Addon connected to plane I sector 3. It is important to use the active terminator resistors(small adapter boards) to terminate the buses. I experienced for short BUS cables (1-1.5meters) there is no need to terminate the lines. For longer cables the noise might disturb the BUS lines.

BUS0 1 short MB(111), BUS1 2 long MBs(113+112), BUS2 1 short MB(121), BUS3 1 short(122), BUS4 2 long MBs(321+311), BUS5 2 short MBs(312+322), BUS6 2 long MBs(213+212), BUS7 1 short MB(222), BUS8 1 short(211), BUS9 1 short(221).

Initialization:

jamv2_reg -aRUN_XILINX_PROC /home/hadaq/mdc_addon/trb_mdc_test7.stapl

jamv2_addon-aRUN_XILINX_PROC /home/hadaq/mdc_addon/readout_test_2_clkto_trb_10bus_busn_mux.stapl

rw_mdc_addon w 0 7 931C261 (MB number: fixed)

rw_mdc_addon w 0 0E 0B100E

rw_trbv2 w 0 6 106

readout_nodma_trbv2 -w 32000 -o UDP:140.181.93.18:30043

Here some events: normal and calibration data:

 
META FILEATTACHMENT attr="" comment="3 bus normal event" date="1217323113" name="3bus_normal_event.txt" path="3bus_normal_event.txt" size="2254" user="AttilioTarantola" version="1.1"
META FILEATTACHMENT attr="" comment="data from 10 buses" date="1217599425" name="data_10buses.txt" path="data_10buses.txt" size="4167" user="AttilioTarantola" version="1.1"
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META FILEATTACHMENT attr="" comment="planeI sector3 data" date="1218555726" name="10_bus_plane1_sector3.txt" path="10_bus_plane1_sector3.txt" size="25156" user="AttilioTarantola" version="1.1"
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META TOPICPARENT name="DaqUpgradeMDCOverview"
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Configuration register in the Virtex on Addon. Write/read these with ./rw_mdc_addon

r/w device address bits
r/w 0 06 31-10: not used 9-0: when 1 BUS disable, when 0 bus enable. Each bit corresponds to 1 BUS
Changed:
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r/w 0 07 31-30: not used 29-0: 3 bits define how many MB are connected to one BUS, 001: 1 short; 010: 2 short; 011: 1 long; 100:2 long. Bits 3-0 define BUS0,Bits 7-4 define BUS1,...
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r/w 0 07 31-30: not used 29-0: 3 bits define how many MB are connected to one BUS, "001": 1 short; "010": 2 short; "011": 1 long; "100":2 long. Bits 3-0 define BUS0, Bits 7-4 define BUS1,...
 
r/w 0 0E 31-25: not used 24-21: x"0" enable internal common stop, x"1" enable external common stop 19-16: when set to B, config. data is loaded into TDCs 15-4: (N-number) downscaling for CAL trigger 3-0: C (only calibration is enabled), D(calibration is disabled), E(send one calibration trigger every N-number of normal trigger)
r/w 5: RAM->BUS0 address and data are defined in the configuration file
r/w 6: RAM->BUS1 address and data are defined in the configuration file
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r/w device address bits
w 0:Virtex on TRB 6 106: enable internal OR external trigger. 100: enable only external trigger
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Debug registers in the Virtex on Addon

r/w device address bits
r 0 1 31-28:not used 27-20:number of received token back 19-12: number of calibration trigger processed 11-4:number of processed trigger 3-0: State machine trigger_distributor.vhd: x"1" idle state (wait for triggers), x"2" wait token state, x"6" wait until TDCs initialization finished, x"9" wait token for calibration event
 

Important pins on the Addon

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META TOPICPARENT name="DaqUpgradeMDCOverview"
-- AttilioTarantola - 05 Aug 2008
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  ADO_TTL5: calibration trigger input for TRB(LVTTL). If not used put this to GND.

J1: is Common Stop input(LVTTL).
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One can see the CMS in LA(20) in HPLA6, after it passed through the Virtex.
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One can see the CMS in LA(23) in HPLA6, after it passed through the Virtex.

HPLA6:

LA(16) <= CLK;

LA(17) <= trigger_in_i; --trigger in(respect to Addon)

LA(18) <= init_all_buses_i(0);

LA(19) <= A_RDM; --BUS0 token out (respect Addon)

LA(20) <= A_RDO; --BUS0 token in (respect Addon)

LA(21) <= data_valid_i; --to TRB for data

LA(22) <= token_to_trb_i;

LA(23) <= external_cms_i;

LA(24) <= data_bus_out_i(0); --Addon-TRB data bus

LA(25) <= data_bus_out_i(1);

LA(26) <= data_bus_out_i(2);

LA(27) <= data_bus_out_i(3);

LA(28) <= data_bus_out_i(4);

LA(29) <= data_bus_out_i(5);

LA(30) <= data_bus_out_i(6);

LA(31) <= data_bus_out_i(7);
 

Display

The display on Addon shows the calibration trigger number (in hexadecimal numbers).
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FPGA Device Utilization Summary

Device speed data version:  "PRODUCTION 1.68 2007-11-08".

Device Utilization Summary:

Number of BUFGs                           1 out of 32      3%

Number of External IOBs                 498 out of 640    77%

Number of LOCed IOBs                 498 out of 498   100%

Number of External IOBMs                  1 out of 224     1%

Number of LOCed IOBMs                  1 out of 1     100%

Number of External IOBSs                  1 out of 224     1%

Number of LOCed IOBSs                  1 out of 1     100%

Number of RAMB16s                        70 out of 96     72%

Number of Slices                       6118 out of 18432  33%

Number of SLICEMs                      0 out of 9216    0%

 

Test in the laboratory

-- AttilioTarantola - 01 Aug 2008
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META TOPICPARENT name="DaqUpgradeMDCOverview"
-- AttilioTarantola - 05 Aug 2008
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  J1: is Common Stop input(LVTTL). One can see the CMS in LA(20) in HPLA6, after it passed through the Virtex.
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Display

The display on Addon shows the calibration trigger number (in hexadecimal numbers).
 

Test in the laboratory

-- AttilioTarantola - 01 Aug 2008
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META TOPICPARENT name="DaqUpgradeMDCOverview"
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-- AttilioTarantola - 28 Jul 2008
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-- AttilioTarantola - 05 Aug 2008
 
Changed:
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The software configures and takes data from 3 buses. By default all 3 buses are enabled. After you loaded the firmware, the chip reset itself and all state machine go in idle states.
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The software configures and takes data from 10 buses. By default all 10 buses are enabled. After you loaded the firmware, the chip reset itself and all state machines go in idle states.
  The description on the configuration register is in the table.

1. login in the ETRAX as ROOT.
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2. program FPGA on TRB: /home/hadaq/jamv2_reg aRUN_XILINX_PROC /home/hadaq/Mdc_addon/trb_mdc_test5.stapl Note: This design has a buffer (LVL1 fifo) which is depth 1024. Do not calibrate all channels together).
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2. program FPGA on TRB: /home/hadaq/jamv2_reg aRUN_XILINX_PROC /home/hadaq/Mdc_addon/trb_mdc_test7.stapl
 

3. set the environment: export DAQ_SETUP=pion9

4. program the FPGA on Add-On:
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/home/hadaq/jamv2_addon -aRUN_XILINX_PROC /home/hadaq/Mdc_addon/readout_test_2_clkto_trb_10bus.stapl
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/home/hadaq/jamv2_addon -aRUN_XILINX_PROC /home/hadaq/Mdc_addon/readout_test_2_clkto_trb_10bus_busn_mux.stapl
 

5. Modify the configuration parameters in the RAMs as you need. Each RAM has a device number: configuration data in RAM0 is loaded in BUS0. You can change the content of RAM0 if you set device number to 5.
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META TOPICPARENT name="DaqUpgradeMDCOverview"
-- AttilioTarantola - 28 Jul 2008
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  J1: is Common Stop input(LVTTL). One can see the CMS in LA(20) in HPLA6, after it passed through the Virtex.
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Test in the laboratory

 
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Here one can see how 1 event from 3 buses looks like * 1 event from 3 buses
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-- AttilioTarantola - 01 Aug 2008
 
Changed:
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BUS0 0x0110005a data from 2 long MB
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I connected all FEE available to the Addon:
 
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BUS1 0x01110012 data from 1 short
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BUS0 1 long MB, BUS1 2 long, BUS2 1 short, BUS3 NO MB connected, BUS4 1 short, BUS5 NO MBs connected, BUS6 2 short, BUS7 NO MBs connected, BUS8 1 short, BUS9 1 short.
 
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BUS2 0x0112001b data from 1 short
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Initialization registers:
 

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./rw_mdc_addon w 0 6 1A8

./rw_mdc_addon w 0 7 8081063

./rw_mdc_addon w 0 0E 0B003D

 

META FILEATTACHMENT attr="" comment="3 bus normal event" date="1217323113" name="3bus_normal_event.txt" path="3bus_normal_event.txt" size="2254" user="AttilioTarantola" version="1.1"
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META FILEATTACHMENT attr="" comment="data from 10 buses" date="1217599425" name="data_10buses.txt" path="data_10buses.txt" size="4167" user="AttilioTarantola" version="1.1"
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1. login in the ETRAX as ROOT.
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2. program FPGA on TRB: /home/hadaq/jamv2_reg -aRUN_XILINX_PROC /home/hadaq/Mdc_addon/trb_mdc_test5.stapl
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2. program FPGA on TRB: /home/hadaq/jamv2_reg aRUN_XILINX_PROC /home/hadaq/Mdc_addon/trb_mdc_test5.stapl Note: This design has a buffer (LVL1 fifo) which is depth 1024. Do not calibrate all channels together).
 

3. set the environment: export DAQ_SETUP=pion9

4. program the FPGA on Add-On:
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/home/hadaq/jamv2_addon -aRUN_XILINX_PROC /home/hadaq/Mdc_addon/readout_test_2_clkto_trb_3bus.stapl
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/home/hadaq/jamv2_addon -aRUN_XILINX_PROC /home/hadaq/Mdc_addon/readout_test_2_clkto_trb_10bus.stapl
 

5. Modify the configuration parameters in the RAMs as you need. Each RAM has a device number: configuration data in RAM0 is loaded in BUS0. You can change the content of RAM0 if you set device number to 5.
Line: 22 to 23
 

7. Set the number of MBs which are connected to each BUS: ./rw_mdc_addon w 0 7 4C. (x"4C" = "001 001 100": 2 long in BUS0, 1 short in BUS1,1 short in BUS2)

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8. enable/disable calibration trigger and load the begin run trigger: ./rw_mdc_addon w 0 0E 0B003E.
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8. Enable/disable calibration trigger and load the begin run trigger: ./rw_mdc_addon w 0 0E 0B003E.
  Here I ask 1 calibraion trigger every x"003" normal trigger, x"B" means begin run trigger and x"0" enable internal common stop.

9. Write in the TRB register which kind of trigger you want to use: ./rw_trbv2 w 0 6 106 (here internal trigger)
Line: 35 to 36
 
r/w 0 06 31-10: not used 9-0: when 1 BUS disable, when 0 bus enable. Each bit corresponds to 1 BUS
r/w 0 07 31-30: not used 29-0: 3 bits define how many MB are connected to one BUS, 001: 1 short; 010: 2 short; 011: 1 long; 100:2 long. Bits 3-0 define BUS0,Bits 7-4 define BUS1,...
r/w 0 0E 31-25: not used 24-21: x"0" enable internal common stop, x"1" enable external common stop 19-16: when set to B, config. data is loaded into TDCs 15-4: (N-number) downscaling for CAL trigger 3-0: C (only calibration is enabled), D(calibration is disabled), E(send one calibration trigger every N-number of normal trigger)
Changed:
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r/w 5: RAM which corrisponds to BUS0 address and data are defined in the configuration file
r/w 6: RAM which corrisponds to BUS1 address and data are defined in the configuration file
r/w 7: RAM which corrisponds to BUS2 address and data are defined in the configuration file
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r/w 5: RAM->BUS0 address and data are defined in the configuration file
r/w 6: RAM->BUS1 address and data are defined in the configuration file
r/w 7: RAM->BUS2 address and data are defined in the configuration file
r/w 8: RAM->BUS3 address and data are defined in the configuration file
r/w 9: RAM->BUS4 address and data are defined in the configuration file
r/w A: RAM->BUS5 address and data are defined in the configuration file
r/w B: RAM->BUS6 address and data are defined in the configuration file
r/w C: RAM->BUS7 address and data are defined in the configuration file
r/w D: RAM->BUS8 address and data are defined in the configuration file
r/w E: RAM->BUS9 address and data are defined in the configuration file
 

Configuration register in the Virtex on TRB. Write/read these with ./rw_trbv2

r/w device address bits
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META TOPICPARENT name="DaqUpgradeMDCOverview"
-- AttilioTarantola - 28 Jul 2008
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7. Set the number of MBs which are connected to each BUS: ./rw_mdc_addon w 0 7 4C. (x"4C" = "001 001 100": 2 long in BUS0, 1 short in BUS1,1 short in BUS2)

Changed:
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8. enable/disable calibration trigger and load the begin run trigger: =./rw_mdc_addon w 0 0E 0B003E.
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8. enable/disable calibration trigger and load the begin run trigger: ./rw_mdc_addon w 0 0E 0B003E.
  Here I ask 1 calibraion trigger every x"003" normal trigger, x"B" means begin run trigger and x"0" enable internal common stop.
Changed:
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9. Write in the TRB register which kind of trigger you want to use: =./rw_trbv2 w 0 6 106 (here internal trigger)
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9. Write in the TRB register which kind of trigger you want to use: ./rw_trbv2 w 0 6 106 (here internal trigger)
 
Changed:
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10. Start readout: ./readout_nodma_trbv2 -w 32000 -o UDP:192.168.0.1:30000
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10. Start readout: ./readout_nodma_trbv2 -w 32000 -o UDP:192.168.0.1:30000
 

Configuration register in the Virtex on Addon. Write/read these with ./rw_mdc_addon

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META TOPICPARENT name="DaqUpgradeMDCOverview"
-- AttilioTarantola - 28 Jul 2008
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  4. program the FPGA on Add-On: /home/hadaq/jamv2_addon -aRUN_XILINX_PROC /home/hadaq/Mdc_addon/readout_test_2_clkto_trb_3bus.stapl
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5. enable/disable the buses: ./rw_mdc_addon w 0 6 5. (x"5" = "101": enable BUS1 and disable BUS0 and BUS2 Note: This bitmask has inverse logic)
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5. Modify the configuration parameters in the RAMs as you need. Each RAM has a device number: configuration data in RAM0 is loaded in BUS0. You can change the content of RAM0 if you set device number to 5.
 
Changed:
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6. set the number of MBs which are connected to each BUS: ./rw_mdc_addon w 0 7 4C. (x"4C" = "001 001 100": 2 long in BUS0, 1 short in BUS1,1 short in BUS2)
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6. Enable/disable the buses: ./rw_mdc_addon w 0 6 5. (x"5" = "101": enable BUS1 and disable BUS0 and BUS2 Note: This bitmask has inverse logic)
 

Changed:
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7. Modify the configuration parameters in the RAMs as you need. Each RAM has a device number: configuration data in RAM0 is loaded in BUS0. You can change the content of RAM0 if you set device number to 5.
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7. Set the number of MBs which are connected to each BUS: ./rw_mdc_addon w 0 7 4C. (x"4C" = "001 001 100": 2 long in BUS0, 1 short in BUS1,1 short in BUS2)
 

8. enable/disable calibration trigger and load the begin run trigger: =./rw_mdc_addon w 0 0E 0B003E. Here I ask 1 calibraion trigger every x"003" normal trigger, x"B" means begin run trigger and x"0" enable internal common stop.
Revision 5
29 Jul 2008 - Main.JoernWuestenfeld
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META TOPICPARENT name="DaqUpgradeMDCOverview"
-- AttilioTarantola - 28 Jul 2008
Line: 16 to 16
  4. program the FPGA on Add-On: /home/hadaq/jamv2_addon -aRUN_XILINX_PROC /home/hadaq/Mdc_addon/readout_test_2_clkto_trb_3bus.stapl
Changed:
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5. enable/disable the buses: ./rw_mdc_addon w 0 6 5. (x"5" = "101": enable BUS1 and disable BUS0 and BUS2)
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5. enable/disable the buses: ./rw_mdc_addon w 0 6 5. (x"5" = "101": enable BUS1 and disable BUS0 and BUS2 Note: This bitmask has inverse logic)
 

6. set the number of MBs which are connected to each BUS: ./rw_mdc_addon w 0 7 4C. (x"4C" = "001 001 100": 2 long in BUS0, 1 short in BUS1,1 short in BUS2)

Changed:
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7. Modify the configuration parameters in the RAMs as you need. Each RAM has a device number: configuration data in RAM0 is loaded in BUS0. You can change the content of RAM0 if you set device number on 5.
>
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7. Modify the configuration parameters in the RAMs as you need. Each RAM has a device number: configuration data in RAM0 is loaded in BUS0. You can change the content of RAM0 if you set device number to 5.
 
Changed:
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8. enable/disable calibration trigger and load the begin run trigger: ./rw_mdc_addon w 0 0E 0B003E.
>
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8. enable/disable calibration trigger and load the begin run trigger: =./rw_mdc_addon w 0 0E 0B003E.
  Here I ask 1 calibraion trigger every x"003" normal trigger, x"B" means begin run trigger and x"0" enable internal common stop.
Changed:
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9. Write in the TRB register which kind of trigger you want to use: ./rw_trbv2 w 0 6 106 (here internal trigger)
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9. Write in the TRB register which kind of trigger you want to use: =./rw_trbv2 w 0 6 106 (here internal trigger)
 

10. Start readout: ./readout_nodma_trbv2 -w 32000 -o UDP:192.168.0.1:30000

Configuration register in the Virtex on Addon. Write/read these with ./rw_mdc_addon

r/w device address bits
Changed:
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r/w 0 06 31-10: not used 9-0: when 1 BUS disable, when 0 bus enable. Each bit correspond to 1 BUS
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r/w 0 06 31-10: not used 9-0: when 1 BUS disable, when 0 bus enable. Each bit corresponds to 1 BUS
 
r/w 0 07 31-30: not used 29-0: 3 bits define how many MB are connected to one BUS, 001: 1 short; 010: 2 short; 011: 1 long; 100:2 long. Bits 3-0 define BUS0,Bits 7-4 define BUS1,...
Changed:
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r/w 0 0E 31-25: not used 24-21: x"0" enable internal common stop, x"1" enable external common stop 19-16: when write B, config. data is loaded into TDCs 15-4: (N-number) downscaling for CAL trigger 3-0: C (only calibration is enabled), D(calibration is disabled), E(send one calibration trigger every N-number of normal trigger)
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r/w 0 0E 31-25: not used 24-21: x"0" enable internal common stop, x"1" enable external common stop 19-16: when set to B, config. data is loaded into TDCs 15-4: (N-number) downscaling for CAL trigger 3-0: C (only calibration is enabled), D(calibration is disabled), E(send one calibration trigger every N-number of normal trigger)
 
r/w 5: RAM which corrisponds to BUS0 address and data are defined in the configuration file
r/w 6: RAM which corrisponds to BUS1 address and data are defined in the configuration file
r/w 7: RAM which corrisponds to BUS2 address and data are defined in the configuration file
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META TOPICPARENT name="DaqUpgradeMDCOverview"
-- AttilioTarantola - 28 Jul 2008
Line: 16 to 16
  4. program the FPGA on Add-On: /home/hadaq/jamv2_addon -aRUN_XILINX_PROC /home/hadaq/Mdc_addon/readout_test_2_clkto_trb_3bus.stapl
Changed:
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5. enable/disable the buses: ./rw_mdc_addon w 0 06 00
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5. enable/disable the buses: ./rw_mdc_addon w 0 6 5. (x"5" = "101": enable BUS1 and disable BUS0 and BUS2)
 
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6. set the number of MBs which are connected to each BUS: ./rw_mdc_addon w 0 7 1
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6. set the number of MBs which are connected to each BUS: ./rw_mdc_addon w 0 7 4C. (x"4C" = "001 001 100": 2 long in BUS0, 1 short in BUS1,1 short in BUS2)
 

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7. Modify the configuration parameters in the RAMs.
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7. Modify the configuration parameters in the RAMs as you need. Each RAM has a device number: configuration data in RAM0 is loaded in BUS0. You can change the content of RAM0 if you set device number on 5.
 
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8. enable/disable calibration trigger and load the begin run trigger: ./rw_mdc_addon w 0 0E B003E
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8. enable/disable calibration trigger and load the begin run trigger: ./rw_mdc_addon w 0 0E 0B003E. Here I ask 1 calibraion trigger every x"003" normal trigger, x"B" means begin run trigger and x"0" enable internal common stop.
 
Changed:
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In this case I ask 1 calibraion trigger every 3 normal trigger. B means begin run trigger.
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9. Write in the TRB register which kind of trigger you want to use: ./rw_trbv2 w 0 6 106 (here internal trigger)
 
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10. Start readout: ./readout_nodma_trbv2 -w 32000 -o UDP:192.168.0.1:30000
 

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Configuration register in the Virtex

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Configuration register in the Virtex on Addon. Write/read these with ./rw_mdc_addon

 
r/w device address bits
r/w 0 06 31-10: not used 9-0: when 1 BUS disable, when 0 bus enable. Each bit correspond to 1 BUS
r/w 0 07 31-30: not used 29-0: 3 bits define how many MB are connected to one BUS, 001: 1 short; 010: 2 short; 011: 1 long; 100:2 long. Bits 3-0 define BUS0,Bits 7-4 define BUS1,...
Changed:
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r/w 0 0E 31-20: not used 19-16: when write B, config. data is loaded into TDCs 15-4: (N-number) downscaling for CAL trigger 3-0: C (only calibration is enabled), D(calibration is disabled), E(send one calibration trigger every N-number of normal trigger)
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r/w 0 0E 31-25: not used 24-21: x"0" enable internal common stop, x"1" enable external common stop 19-16: when write B, config. data is loaded into TDCs 15-4: (N-number) downscaling for CAL trigger 3-0: C (only calibration is enabled), D(calibration is disabled), E(send one calibration trigger every N-number of normal trigger)
 
r/w 5: RAM which corrisponds to BUS0 address and data are defined in the configuration file
r/w 6: RAM which corrisponds to BUS1 address and data are defined in the configuration file
r/w 7: RAM which corrisponds to BUS2 address and data are defined in the configuration file
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Configuration register in the Virtex on TRB. Write/read these with ./rw_trbv2

r/w device address bits
w 0:Virtex on TRB 6 106: enable internal OR external trigger. 100: enable only external trigger
 

Important pins on the Addon

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HPLA1:
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HPLA1:
 

ADO_TTL8: TRB busy output (LVTTL)
Line: 47 to 54
 

ADO_TTL5: calibration trigger input for TRB(LVTTL). If not used put this to GND.
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J1: is Common Stop input(LVTTL).
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J1: is Common Stop input(LVTTL).
  One can see the CMS in LA(20) in HPLA6, after it passed through the Virtex.
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Here one can see how 1 event from 3 buses looks like * 1 event from 3 buses

BUS0 0x0110005a data from 2 long MB

BUS1 0x01110012 data from 1 short

BUS2 0x0112001b data from 1 short

META FILEATTACHMENT attr="" comment="3 bus normal event" date="1217323113" name="3bus_normal_event.txt" path="3bus_normal_event.txt" size="2254" user="AttilioTarantola" version="1.1"
Revision 3
28 Jul 2008 - Main.AttilioTarantola
Line: 1 to 1
 
META TOPICPARENT name="DaqUpgradeMDCOverview"
-- AttilioTarantola - 28 Jul 2008
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  The software configures and takes data from 3 buses. By default all 3 buses are enabled. After you loaded the firmware, the chip reset itself and all state machine go in idle states.
Line: 17 to 18
 

5. enable/disable the buses: ./rw_mdc_addon w 0 06 00
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6. set the number of MBs which are connected to BUSES: ./rw_mdc_addon w 0 7 1
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6. set the number of MBs which are connected to each BUS: ./rw_mdc_addon w 0 7 1

7. Modify the configuration parameters in the RAMs.
 

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8. enable/disable calibration trigger and load the begin run trigger: ./rw_mdc_addon w 0 0E B003E
 
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7. enable/disable calibration trigger and load the begin run trigger: ./rw_mdc_addon w 0 0E B003E
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In this case I ask 1 calibraion trigger every 3 normal trigger. B means begin run trigger.
 

Line: 33 to 37
 
r/w 6: RAM which corrisponds to BUS1 address and data are defined in the configuration file
r/w 7: RAM which corrisponds to BUS2 address and data are defined in the configuration file
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Important pins on the Addon

HPLA1:

ADO_TTL8: TRB busy output (LVTTL)

ADO_TTL6: trigger input for TRB(LVTTL)

ADO_TTL5: calibration trigger input for TRB(LVTTL). If not used put this to GND.

J1: is Common Stop input(LVTTL). One can see the CMS in LA(20) in HPLA6, after it passed through the Virtex.
Revision 2
28 Jul 2008 - Main.AttilioTarantola
Line: 1 to 1
 
META TOPICPARENT name="DaqUpgradeMDCOverview"
Changed:
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-- AttilioTarantola - 25 Jul 2008 fff
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-- AttilioTarantola - 28 Jul 2008 The software configures and takes data from 3 buses. By default all 3 buses are enabled. After you loaded the firmware, the chip reset itself and all state machine go in idle states. The description on the configuration register is in the table.

1. login in the ETRAX as ROOT.

2. program FPGA on TRB: = /home/hadaq/jamv2_reg -aRUN_XILINX_PROC /home/hadaq/Mdc_addon/trb_mdc_test5.stapl=

3. set the environment: export DAQ_SETUP=pion9

4. program the FPGA on Add-On: /home/hadaq/jamv2_addon -aRUN_XILINX_PROC /home/hadaq/Mdc_addon/readout_test_2_clkto_trb_3bus.stapl

5. enable/disable the buses: ./rw_mdc_addon w 0 06 00

6. set the number of MBs which are connected to BUSES: ./rw_mdc_addon w 0 7 1

7. enable/disable calibration trigger and load the begin run trigger: ./rw_mdc_addon w 0 0E B003E

Configuration register in the Virtex

r/w device address bits
r/w 0 06 31-10: not used 9-0: when 1 BUS disable, when 0 bus enable. Each bit correspond to 1 BUS
r/w 0 07 31-30: not used 29-0: 3 bits define how many MB are connected to one BUS, 001: 1 short; 010: 2 short; 011: 1 long; 100:2 long. Bits 3-0 define BUS0,Bits 7-4 define BUS1,...
r/w 0 0E 31-20: not used 19-16: when write B, config. data is loaded into TDCs 15-4: (N-number) downscaling for CAL trigger 3-0: C (only calibration is enabled), D(calibration is disabled), E(send one calibration trigger every N-number of normal trigger)
r/w 5: RAM which corrisponds to BUS0 address and data are defined in the configuration file
r/w 6: RAM which corrisponds to BUS1 address and data are defined in the configuration file
r/w 7: RAM which corrisponds to BUS2 address and data are defined in the configuration file
 
 
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