Difference: MarekPalka (1 vs. 5)

Revision 5
27 Jun 2007 - Main.MarekPalka
Line: 1 to 1
 
META TOPICPARENT name="TRBProgressReports"
-- MarekPalka - 02 Mar 2007

MarekPalka

Line: 37 to 37
 
      • Whole code needs to be cleaned and corrected (e.g. IO register in synplify)
        It was possible to achieve:
10 kHz with 80 words per event (apr. 40kHz with 20 words per event)
Changed:
<
<
>
>
  • Communication protocol between ETRAX-FS and FPGA done
 
  • MU V2:
    • hardware: MU concentrator, 1.5 GBit link - optical link test started
    • software: MU algorithm - same as old MU, but in VME-CPU not started
Revision 4
24 May 2007 - Main.MarekPalka
Line: 1 to 1
 
META TOPICPARENT name="TRBProgressReports"
-- MarekPalka - 02 Mar 2007

MarekPalka

Line: 17 to 17
 
    • simulation done
    • hardware tests started
  • New TRB V2 VHDL code almost finished . Entities:
Deleted:
<
<
    • sdram_interface.vhd from Xilinx (MIG - memory interface genarator) not started
 
    • tdc_interface.vhd almost finished (has been simulated and tested)
    • lvl1_fifo.vhd done (has been simulated and tested)
    • lvl1_lvl2_busy.vhd - almost finished (has been simulated and tested)
Line: 28 to 27
 
    • dtu_interface.vhd - almost finished
    • sdram_interafce.vhd - started - it is possible to write and read (problems with addressing), no burst, still under tests
    • connection with mdc addon - started - it was possible to see some unreal data (self triggering mode - I'm treating mdc addon as TDC's on TRB - send token and wait for data)
Added:
>
>
    • ctu.vhd - started - code is written, now I have to test it...
 
    • other entities (SPI...)
    • actual situation:
      • it was possible to read TDC ID and program with setup data, there is error in JTAG interface - this is not destroying the data(jtag interface error) .. ,
Changed:
<
<
      • optical transmition is ok,
        together with Radek we wrote comunication protocol and it is working
>
>
      • optical transmition is ok,
      • together with Radek we wrote comunication protocol and it is working
 
      • All VHDL programs were connected, it was possible to download the data from the TDC's with ETRAX(Radek's part) and with included HADES DAQ(Radek's part)
      • Whole code needs to be cleaned and corrected (e.g. IO register in synplify)
        It was possible to achieve:
Revision 3
18 May 2007 - Main.MarekPalka
Line: 1 to 1
 
META TOPICPARENT name="TRBProgressReports"
-- MarekPalka - 02 Mar 2007

MarekPalka

Line: 24 to 24
 
    • trigger_logic.vhd - almost finished (has been simulated and tested)
    • etrax_interface.vhd - almost finished (has been simulated and tested)
    • tlk_interface.vhd - almost finished (has been simulated and tested)
Changed:
<
<
    • dsp_interface.vhd - started
    • dtu_interface.vhd - started
>
>
    • dsp_interface.vhd - started (it is possible to write and read from the DSP
    • dtu_interface.vhd - almost finished
    • sdram_interafce.vhd - started - it is possible to write and read (problems with addressing), no burst, still under tests
    • connection with mdc addon - started - it was possible to see some unreal data (self triggering mode - I'm treating mdc addon as TDC's on TRB - send token and wait for data)
 
    • other entities (SPI...)
    • actual situation:
Changed:
<
<
      • it was possible to read TDC ID and program with setup data, there is error in JTAG interface - this is not destroying the data .. ,
      • optical transmition seems to be ok:error pin on TLK2501 during transmition is inactivate,
        together with Radek we wrote comunication protocol and it is working
      • FPGA is "eating" one word in the data (additional data word overwrites header from TDC
>
>
      • it was possible to read TDC ID and program with setup data, there is error in JTAG interface - this is not destroying the data(jtag interface error) .. ,
      • optical transmition is ok,
        together with Radek we wrote comunication protocol and it is working
 
      • All VHDL programs were connected, it was possible to download the data from the TDC's with ETRAX(Radek's part) and with included HADES DAQ(Radek's part)
      • Whole code needs to be cleaned and corrected (e.g. IO register in synplify)
        It was possible to achieve:
Revision 2
14 Mar 2007 - Main.MarekPalka
Line: 1 to 1
 
META TOPICPARENT name="TRBProgressReports"
-- MarekPalka - 02 Mar 2007

MarekPalka

Line: 25 to 25
 
    • etrax_interface.vhd - almost finished (has been simulated and tested)
    • tlk_interface.vhd - almost finished (has been simulated and tested)
    • dsp_interface.vhd - started
Changed:
<
<
    • dtu_interface.vhd - not started
>
>
    • dtu_interface.vhd - started
 
    • other entities (SPI...)
    • actual situation:
      • it was possible to read TDC ID and program with setup data, there is error in JTAG interface - this is not destroying the data .. ,
Line: 39 to 39
 
  • MU V2:
    • hardware: MU concentrator, 1.5 GBit link - optical link test started
    • software: MU algorithm - same as old MU, but in VME-CPU not started
Changed:
<
<
  • TRB V1 tests of all channels started
>
>
  • TRB V1 tests of all channels started (test setup - JIN1 LVTTL on pin 9, JOUT1 4th pair)
 
  • TRB network - some cosmetics needed - started
  • Changing htrbbaseupacker.cc (new header) - started - needs verification with hld file with new data format
 
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