Difference: NewCTS (1 vs. 24)

Revision 24
18 May 2010 - Main.MarekPalka
Line: 1 to 1
 
META TOPICPARENT name="DaqNetwork"

CTS and Trigger Logic addresses

Line: 67 to 67
 
dc 7 Enable daily Shower calibration trigger
dc 11 downto 8 Select frequency for generated trigger,781.25kHz/(2^value)
89 - trigger logic debug out
Changed:
<
<
ba -8b all bits scalers out
>
>
9a -bb all bits scalers out
 

More detailed description can be found : .... (pdf files)
Revision 23
06 May 2010 - Main.MarekPalka
Line: 1 to 1
 
META TOPICPARENT name="DaqNetwork"

CTS and Trigger Logic addresses

Line: 34 to 34
 
c5 27 downto 20 how many LVL1 trigger has to pass to send LVL2 trigger
c5 28 trigger on rising edge
c5 29 not used
Changed:
<
<
c5 30 enable connection to vulom
>
>
c5 30 enable connection to trigger box
 
c5 31 make double APV pulse
c6 7 downto 0 LVL2 downscale
c6 27 downto 8 frequency of self triggering : 50MHz/value
Revision 22
03 May 2010 - Main.MarekPalka
Line: 1 to 1
 
META TOPICPARENT name="DaqNetwork"

CTS and Trigger Logic addresses

Line: 30 to 30
 
93 31 downto 24 CTS fifo data counter a
c3 4 disable readout on etrax
c5 15 downto 0 enable individual triggers:
(4 downto 0) - LVDS(4 downto 0) - corresponds to ado_lv(9 downto 0) on the trbv2 schematics
(9 downto 5) - LVTTL(20 downto 16) - corresponds to ado_ttl(20 downto 16) on the trbv2 schematics
(10) trigger form fast reference trigger - corresponds to Vir_Trig on the trbv2 schematics
(11) self triggering (internal generator)
(12) coincidence LVDS(0) and LVDS(1)
(13) Trigger from C5(28) register
(14) coincidence LVTTL(0) and LVTTL(1)
(15) coincidence LVTTL(2) and LVTTL(3)
Depends which input is enabled there is corresponding trigger code 0 - x0xf , 1 - x0xe, 2 - 0xd ...
Changed:
<
<
c5 17 downto 16 change source of LVL2 trigger:
"00" - auto
"01" - LVDS lines
"10"- loacal source
>
>
c5 17 downto 16 change source of LVL2 trigger:
"00" - auto
"01" - LVDS lines
"10"- local source
 
c5 27 downto 20 how many LVL1 trigger has to pass to send LVL2 trigger
c5 28 trigger on rising edge
c5 29 not used
Line: 39 to 39
 
c6 7 downto 0 LVL2 downscale
c6 27 downto 8 frequency of self triggering : 50MHz/value
c6 31 downto 28 length of timing trigger : 100ns + value*10ns (when is value< 7), when value > 6 time = (value - 7) * 10ns
Added:
>
>
c7 4 downto 0 if c7(4)=1 the lvl1 trigger type equals c7(3 downto 0) else type is defined internally or by trigger box
 
c8 13 downto 0 lvl1 trigger information 13 downto 0
Added:
>
>
c9 31 downto 0 how many events is send before next ID of IP address is changed, when equals 0 then default is taken from c10(3 downto 0)
c11-c10 all bits divided into nibles First nible ( c10(3 downto 0) ) is the first ID of the EB IP and so on (16 IDs)
 

Address range from 0x80 to 0xBF is for read only registers above 0xc0 is for read/write registers.
Revision 21
29 Apr 2010 - Main.MarekPalka
Line: 1 to 1
 
META TOPICPARENT name="DaqNetwork"

CTS and Trigger Logic addresses

Line: 7 to 7
 

CTS

Address Bit range Meaning
Changed:
<
<
91 15 downto 0 lvl1 trigger tag
>
>
91 15 downto 0 lvl1 trigger number
 
91 19 downto 16 lvl1 trigger code
91 20 lvl1 cts busy
91 21 lvl1 trbnet busy
91 22 lvl1 local busy
Changed:
<
<
91 23 self trigger coounter(8)
>
>
91 23 lvl1 trigger box busy
 
91 31 downto 24 lvl1 trigger random code
Changed:
<
<
92 15 downto 0 lvl2 trigger tag
92 19 downto 16 lvl2 trigger code
92 20 lvl2 cts busy
92 21 lvl2 trbnet busy
92 22 lvl2 local busy
92 23 downscale counter coounter(2)
92 31 downto 24 lvl2 trigger random code
93 19 downto 0 event rate (accepted triggers/s)
>
>
92 19 downto 0 lvl1 trigger rate (accepted triggers/s)
92 20 apv double pulse busy (RICH)
92 21 lvl1 self trigger
92 25 downto 22 event rate cntr(7,9,11,13) - for diods
92 26 lvl2 cts busy
92 27 lvl2 trbnet busy
92 28 lvl2 local busy
93 0 CTS fifo full b(for random numbers)
93 1 CTS fifo empty b
93 2 CTS fifo full a (trigger code and number)
93 3 CTS fifo empty a
93 11 downto 4 lvl1-lvl2 : difference counter
93 23 downto 12 lvl2 trigger number (11 downto 0)
93 31 downto 24 CTS fifo data counter a
 
c3 4 disable readout on etrax
c5 15 downto 0 enable individual triggers:
(4 downto 0) - LVDS(4 downto 0) - corresponds to ado_lv(9 downto 0) on the trbv2 schematics
(9 downto 5) - LVTTL(20 downto 16) - corresponds to ado_ttl(20 downto 16) on the trbv2 schematics
(10) trigger form fast reference trigger - corresponds to Vir_Trig on the trbv2 schematics
(11) self triggering (internal generator)
(12) coincidence LVDS(0) and LVDS(1)
(13) Trigger from C5(28) register
(14) coincidence LVTTL(0) and LVTTL(1)
(15) coincidence LVTTL(2) and LVTTL(3)
Depends which input is enabled there is corresponding trigger code 0 - x0xf , 1 - x0xe, 2 - 0xd ...
c5 17 downto 16 change source of LVL2 trigger:
"00" - auto
"01" - LVDS lines
"10"- loacal source
Revision 20
29 Apr 2010 - Main.MichaelTraxler
Line: 1 to 1
 
META TOPICPARENT name="DaqNetwork"

CTS and Trigger Logic addresses

Revision 19
27 Apr 2010 - Main.MarekPalka
Line: 1 to 1
 
META TOPICPARENT name="DaqNetwork"

CTS and Trigger Logic addresses

Line: 23 to 23
 
92 31 downto 24 lvl2 trigger random code
93 19 downto 0 event rate (accepted triggers/s)
c3 4 disable readout on etrax
Changed:
<
<
c5 15 downto 0 enable individual triggers:
(4 downto 0) - LVDS(4 downto 0) - corresponds to ado_lv(9 downto 0) on the trbv2 schematics
(9 downto 5) - LVTTL(20 downto 16) - corresponds to ado_ttl(20 downto 16) on the trbv2 schematics
(10) trigger form fast reference trigger - corresponds to Vir_Trig on the trbv2 schematics
(11) self triggering (internal generator)
(12) coincidence LVDS(0) and LVDS(1)
(13) coincidence LVDS(2) and LVDS(3)
(14) coincidence LVTTL(0) and LVTTL(1)
(15) coincidence LVTTL(2) and LVTTL(3)
Depends which input is enabled there is corresponding trigger code 0 - x0xf , 1 - x0xe, 2 - 0xd ...
>
>
c5 15 downto 0 enable individual triggers:
(4 downto 0) - LVDS(4 downto 0) - corresponds to ado_lv(9 downto 0) on the trbv2 schematics
(9 downto 5) - LVTTL(20 downto 16) - corresponds to ado_ttl(20 downto 16) on the trbv2 schematics
(10) trigger form fast reference trigger - corresponds to Vir_Trig on the trbv2 schematics
(11) self triggering (internal generator)
(12) coincidence LVDS(0) and LVDS(1)
(13) Trigger from C5(28) register
(14) coincidence LVTTL(0) and LVTTL(1)
(15) coincidence LVTTL(2) and LVTTL(3)
Depends which input is enabled there is corresponding trigger code 0 - x0xf , 1 - x0xe, 2 - 0xd ...
 
c5 17 downto 16 change source of LVL2 trigger:
"00" - auto
"01" - LVDS lines
"10"- loacal source
c5 27 downto 20 how many LVL1 trigger has to pass to send LVL2 trigger
Changed:
<
<
c5 29 downtto 28 not used
>
>
c5 28 trigger on rising edge
c5 29 not used
 
c5 30 enable connection to vulom
c5 31 make double APV pulse
c6 7 downto 0 LVL2 downscale
Revision 18
23 Apr 2010 - Main.MarekPalka
Line: 1 to 1
 
META TOPICPARENT name="DaqNetwork"

CTS and Trigger Logic addresses

Added:
>
>
To all register when accessing vi trbnet add offset A0
 

CTS

Address Bit range Meaning
Line: 42 to 44
 

HADES Trigger Logic

Added:
>
>
Address Bit range Meaning
cc 31 downto 0 input enables
d0 c16 - c13 all bits downscale, each nibble corresponds to one input
d4 - d1 all bits width, each nibble corresponds to one input
d9 31 downto 0 TS gating disable
da 31 downto 0 trigger out enable
db 23 downto 0 multiplexer out selsect
dc 4 downto 0 if c28(4)=0 then normal trigger selection else trigger code = c(28)(3 downto 0)
dc 5 MDC callibration trigger disable
dc 6 Force Shower calibration trigger
dc 7 Enable daily Shower calibration trigger
dc 11 downto 8 Select frequency for generated trigger,781.25kHz/(2^value)
89 - trigger logic debug out
ba -8b all bits scalers out

More detailed description can be found : .... (pdf files)
 

Other settings

Address Bit range Meaning
c8 13 downto 0 trigger information in
Added:
>
>
cb - ca all 32 bits IP LUT each nibble corresponds to given IP address, the CTS is deciding to which EB current event should go (round robin)
 

How to start readout on CTS with DMA readout

Ensure You have newest kernel : hadeb05:~/soft/devboard-R2_20/.
Line: 72 to 91
  lxhadesdaq:/var/diskless/etrax_fs/bin
lxhadesdaq:/var/diskless/etrax_fs/develop_board
Changed:
<
<
In case of bugs (there are for sure), problems, questions contact with Marek : m.palka@gsi.de :)
>
>
In case of bugs , problems, questions contact with Marek : m.palka@gsi.de
 

Revision 17
23 Apr 2010 - Main.MarekPalka
Line: 1 to 1
 
META TOPICPARENT name="DaqNetwork"
Changed:
<
<

Status and control registers

>
>

CTS and Trigger Logic addresses

CTS

 

Address Bit range Meaning
91 15 downto 0 lvl1 trigger tag
Line: 33 to 35
  Address range from 0x80 to 0xBF is for read only registers above 0xc0 is for read/write registers.

APV signal is on ADO_LV 52(positive) and 53(negative)
Changed:
<
<
Timieng trigger out: ADO_LV 54(p) 55(n)
>
>
Timing trigger out: ADO_LV 54(p) 55(n)
  lvl1 busy out ADO_LV 56(p) 57(n)
lvl2 busy out ADO_LV 58(p) 59(n)
40 MHz clock out ADO_LV 60(p) 61(n)
Added:
>
>

HADES Trigger Logic

Other settings

Address Bit range Meaning
c8 13 downto 0 trigger information in
 

How to start readout on CTS with DMA readout

Ensure You have newest kernel : hadeb05:~/soft/devboard-R2_20/.
If you have it then run following commands :
Revision 16
02 Mar 2010 - Main.MarekPalka
Line: 1 to 1
 
META TOPICPARENT name="DaqNetwork"

Status and control registers

Line: 18 to 18
 
92 23 downscale counter coounter(2)
92 31 downto 24 lvl2 trigger random code
93 19 downto 0 event rate (accepted triggers/s)
Added:
>
>
c3 4 disable readout on etrax
 
c5 15 downto 0 enable individual triggers:
(4 downto 0) - LVDS(4 downto 0) - corresponds to ado_lv(9 downto 0) on the trbv2 schematics
(9 downto 5) - LVTTL(20 downto 16) - corresponds to ado_ttl(20 downto 16) on the trbv2 schematics
(10) trigger form fast reference trigger - corresponds to Vir_Trig on the trbv2 schematics
(11) self triggering (internal generator)
(12) coincidence LVDS(0) and LVDS(1)
(13) coincidence LVDS(2) and LVDS(3)
(14) coincidence LVTTL(0) and LVTTL(1)
(15) coincidence LVTTL(2) and LVTTL(3)
Depends which input is enabled there is corresponding trigger code 0 - x0xf , 1 - x0xe, 2 - 0xd ...
c5 17 downto 16 change source of LVL2 trigger:
"00" - auto
"01" - LVDS lines
"10"- loacal source
c5 27 downto 20 how many LVL1 trigger has to pass to send LVL2 trigger
Revision 15
02 Mar 2010 - Main.MarekPalka
Line: 1 to 1
 
META TOPICPARENT name="DaqNetwork"

Status and control registers

Line: 27 to 27
 
c6 7 downto 0 LVL2 downscale
c6 27 downto 8 frequency of self triggering : 50MHz/value
c6 31 downto 28 length of timing trigger : 100ns + value*10ns (when is value< 7), when value > 6 time = (value - 7) * 10ns
Added:
>
>
c8 13 downto 0 lvl1 trigger information 13 downto 0
 

Address range from 0x80 to 0xBF is for read only registers above 0xc0 is for read/write registers.
Revision 14
31 Dec 2009 - Main.JanMichel
Line: 1 to 1
Changed:
<
<
META TOPICPARENT name="TriggerDistribution"
>
>
META TOPICPARENT name="DaqNetwork"
 

Status and control registers

Address Bit range Meaning
Revision 13
20 Oct 2009 - Main.MarekPalka
Line: 1 to 1
 
META TOPICPARENT name="TriggerDistribution"

Status and control registers

Line: 36 to 36
  lvl2 busy out ADO_LV 58(p) 59(n)
40 MHz clock out ADO_LV 60(p) 61(n)
Changed:
<
<

How to start readout on CTS with DMA readout - this version is close to submit try it on your risk smile

>
>

How to start readout on CTS with DMA readout

  Ensure You have newest kernel : hadeb05:~/soft/devboard-R2_20/.
If you have it then run following commands :
killall readout_dma
Revision 12
20 Oct 2009 - Main.MarekPalka
Line: 1 to 1
 
META TOPICPARENT name="TriggerDistribution"

Status and control registers

Line: 18 to 18
 
92 23 downscale counter coounter(2)
92 31 downto 24 lvl2 trigger random code
93 19 downto 0 event rate (accepted triggers/s)
Changed:
<
<
c5 15 downto 0 enable individual triggers:
(4 downto 0) - LVDS(4 downto 0) - corresponds to ado_lv(9 downto 0) on the trbv2 schematics
(4 downto 0) - LVTTL(20 downto 16) - corresponds to ado_ttl(20 downto 16) on the trbv2 schematics
(10) trigger form fast reference trigger - corresponds to Vir_Trig on the trbv2 schematics
(11) self triggering (internal generator)
(12) coincidence LVDS(0) and LVDS(1)
(13) coincidence LVDS(2) and LVDS(3)
(14) coincidence LVTTL(0) and LVTTL(1)
(15) coincidence LVTTL(2) and LVTTL(3)
>
>
c5 15 downto 0 enable individual triggers:
(4 downto 0) - LVDS(4 downto 0) - corresponds to ado_lv(9 downto 0) on the trbv2 schematics
(9 downto 5) - LVTTL(20 downto 16) - corresponds to ado_ttl(20 downto 16) on the trbv2 schematics
(10) trigger form fast reference trigger - corresponds to Vir_Trig on the trbv2 schematics
(11) self triggering (internal generator)
(12) coincidence LVDS(0) and LVDS(1)
(13) coincidence LVDS(2) and LVDS(3)
(14) coincidence LVTTL(0) and LVTTL(1)
(15) coincidence LVTTL(2) and LVTTL(3)
Depends which input is enabled there is corresponding trigger code 0 - x0xf , 1 - x0xe, 2 - 0xd ...
 
c5 17 downto 16 change source of LVL2 trigger:
"00" - auto
"01" - LVDS lines
"10"- loacal source
c5 27 downto 20 how many LVL1 trigger has to pass to send LVL2 trigger
c5 29 downtto 28 not used
Revision 11
24 Aug 2009 - Main.MarekPalka
Line: 1 to 1
 
META TOPICPARENT name="TriggerDistribution"

Status and control registers

Line: 42 to 42
  killall readout_dma
rmmod readoutdma_module
/home/hadaq/jamv2_reg -aRUN_XILINX_PROC /home/hadaq/develop_board/hades_cts_trb.stapl
Changed:
<
<
rw_portA w 0x0000
>
>
rw_portA w 0x0000
  rw_portB r
rw_portC r
insmod /home/hadaq/readoutdma_module.ko
Revision 10
21 Aug 2009 - Main.MarekPalka
Line: 1 to 1
 
META TOPICPARENT name="TriggerDistribution"

Status and control registers

Line: 42 to 42
  killall readout_dma
rmmod readoutdma_module
/home/hadaq/jamv2_reg -aRUN_XILINX_PROC /home/hadaq/develop_board/hades_cts_trb.stapl
Added:
>
>
rw_portA w 0x0000
  rw_portB r
rw_portC r
insmod /home/hadaq/readoutdma_module.ko
Line: 50 to 51
  sleep 4
rw_trbv2 w 0 c4 0x35f
sleep 10

Changed:
<
<
rw_trbv2 w 0 c2 80000000
rw_trbv2 w 0 c3 00000100
>
>
rw_trbv2 w 0 c2 80000000 # ads header (it will be removed - not necessary )
rw_trbv2 w 0 c3 00000100 # enable blinking diods
  rw_trbv2 w 0 c6 8000
rw_trbv2 w 0 c5 800
Revision 9
21 Aug 2009 - Main.MarekPalka
Line: 1 to 1
 
META TOPICPARENT name="TriggerDistribution"

Status and control registers

Line: 26 to 26
 
c5 31 make double APV pulse
c6 7 downto 0 LVL2 downscale
c6 27 downto 8 frequency of self triggering : 50MHz/value
Changed:
<
<
c6 31 downto 28 length of timing trigger : 100ns + value*10ns
>
>
c6 31 downto 28 length of timing trigger : 100ns + value*10ns (when is value< 7), when value > 6 time = (value - 7) * 10ns
 

Address range from 0x80 to 0xBF is for read only registers above 0xc0 is for read/write registers.
Revision 8
07 Aug 2009 - Main.MarekPalka
Line: 1 to 1
 
META TOPICPARENT name="TriggerDistribution"

Status and control registers

Line: 36 to 36
  lvl2 busy out ADO_LV 58(p) 59(n)
40 MHz clock out ADO_LV 60(p) 61(n)
Changed:
<
<

How to start readout on CTS with old no DMA readout

You need following files (all on lxhadesdaq):
/var/diskless/etrax_fs/develop_board/hades_trb_cts.stapl (last update : 17.33 23.07.2009)
/var/diskless/etrax_fs/bin/jam_trbv2
/var/diskless/etrax_fs/bin/rw_trbv2
/var/diskless/etrax_fs/bin/readout_nodma_trbv2_for_beam

To start you have to login on etrax and run following commands:
killall readout_nodma_trbv2_for_beam
jam_trbv2 --trb -aRUN_XILINX_PROC /home/hadaq/develop_board/hades_trb_cts.stapl
export DAQ_SETUP=trb60
rw_trbv2 w 0 c5 value->look_up ↑ #values are hex numbers
rw_trbv2 w 0 c6 value->look_up ↑ #values are hex numbers
readout_nodma_trbv2_for_beam -w 10000 -o UDP:$eb_ip:$port &

The data is send to the given ip address (eventbuilder).
To collect data it is needed to strart event builder e.g.:
daq_evtbuild -m 1 -d file|null -o ~/test_hld/ -x te -I 1 --ebnum 1 -q 32000000 -S marek
and netmem:
daq_netmem -m 1 -q 3000000 -i UDP:0.0.0.0:$port

How to start readout on CTS with DMA readout - this version is close to submit but not usable now !

Ensure You have new kernel: run command dmesg you should get on output "readoutdma v1.0".
If you have this version or higher then run following commands :
/home/hadaq/jam_trbv2 --trb -aRUN_XILINX_PROC /home/hadaq/designa_name_for_subsystem.stapl
./rw_portB r
./rw_portC r
echo "IOP PROGRAMMING"; insmod /home/hadaq/readoutdma_module10.ko
sleep 1
mm
sleep 1
./readout_dma -w 10000 -o UDP:192.168.0.1:2212 &
>
>

How to start readout on CTS with DMA readout - this version is close to submit try it on your risk smile

Ensure You have newest kernel : hadeb05:~/soft/devboard-R2_20/.
If you have it then run following commands :
killall readout_dma
rmmod readoutdma_module
/home/hadaq/jamv2_reg -aRUN_XILINX_PROC /home/hadaq/develop_board/hades_cts_trb.stapl
rw_portB r
rw_portC r
insmod /home/hadaq/readoutdma_module.ko
sleep 2
readout_dma -w 10000 -o UDP:$eb_ip:34068 &
  sleep 4
Changed:
<
<
echo "FPGA STARTING";
./rw_trbv2 w 0 c2 80000000
./rw_trbv2 w 0 c0 100
./rw_trbv2 w 0 c4 0x35b
./rw_trbv2 w 0 c3 70000002
checkRate.sh
>
>
rw_trbv2 w 0 c4 0x35f
sleep 10

rw_trbv2 w 0 c2 80000000
rw_trbv2 w 0 c3 00000100
rw_trbv2 w 0 c6 8000
rw_trbv2 w 0 c5 800

All files can be founf on :
lxhadesdaq:/var/diskless/etrax_fs/
lxhadesdaq:/var/diskless/etrax_fs/bin
lxhadesdaq:/var/diskless/etrax_fs/develop_board
 
Changed:
<
<

In case of bugs, problems, questions contact with Marek : m.palka@gsi.de smile
>
>
In case of bugs (there are for sure), problems, questions contact with Marek : m.palka@gsi.de :)
 

Revision 7
23 Jul 2009 - Main.MarekPalka
Line: 1 to 1
 
META TOPICPARENT name="TriggerDistribution"

Status and control registers

Line: 38 to 38
 

How to start readout on CTS with old no DMA readout

You need following files (all on lxhadesdaq):
Changed:
<
<
/var/diskless/etrax_fs/develop_board/hades_trb_cts.stapl
>
>
/var/diskless/etrax_fs/develop_board/hades_trb_cts.stapl (last update : 17.33 23.07.2009)
  /var/diskless/etrax_fs/bin/jam_trbv2
/var/diskless/etrax_fs/bin/rw_trbv2
/var/diskless/etrax_fs/bin/readout_nodma_trbv2_for_beam
Revision 6
23 Jul 2009 - Main.MarekPalka
Line: 1 to 1
 
META TOPICPARENT name="TriggerDistribution"

Status and control registers

Line: 31 to 31
  Address range from 0x80 to 0xBF is for read only registers above 0xc0 is for read/write registers.

APV signal is on ADO_LV 52(positive) and 53(negative)
Changed:
<
<
Timieng trigger: ADO_LV 54(p) 55(n)
lvl1 busy ADO_LV 56(p) 57(n)
lvl2 busy ADO_LV 58(p) 59(n)
>
>
Timieng trigger out: ADO_LV 54(p) 55(n)
lvl1 busy out ADO_LV 56(p) 57(n)
lvl2 busy out ADO_LV 58(p) 59(n)
40 MHz clock out ADO_LV 60(p) 61(n)
 

How to start readout on CTS with old no DMA readout

You need following files (all on lxhadesdaq):
Revision 5
23 Jul 2009 - Main.MarekPalka
Line: 1 to 1
 
META TOPICPARENT name="TriggerDistribution"

Status and control registers

Line: 18 to 18
 
92 23 downscale counter coounter(2)
92 31 downto 24 lvl2 trigger random code
93 19 downto 0 event rate (accepted triggers/s)
Changed:
<
<
c5 15 downto 0 enable individual triggers:
(4 downto 0) - LVDS(4 downto 0)
(4 downto 0) - LVTTL(20 downto 16)
(10) trigger form fast reference trigger(LVDS on board)
(11) self triggering (internal generator)
(12) coincidence LVDS(0) and LVDS(1)
(13) coincidence LVDS(2) and LVDS(3)
(14) coincidence LVTTL(0) and LVTTL(1)
(15) coincidence LVTTL(2) and LVTTL(3)
>
>
c5 15 downto 0 enable individual triggers:
(4 downto 0) - LVDS(4 downto 0) - corresponds to ado_lv(9 downto 0) on the trbv2 schematics
(4 downto 0) - LVTTL(20 downto 16) - corresponds to ado_ttl(20 downto 16) on the trbv2 schematics
(10) trigger form fast reference trigger - corresponds to Vir_Trig on the trbv2 schematics
(11) self triggering (internal generator)
(12) coincidence LVDS(0) and LVDS(1)
(13) coincidence LVDS(2) and LVDS(3)
(14) coincidence LVTTL(0) and LVTTL(1)
(15) coincidence LVTTL(2) and LVTTL(3)
 
c5 17 downto 16 change source of LVL2 trigger:
"00" - auto
"01" - LVDS lines
"10"- loacal source
c5 27 downto 20 how many LVL1 trigger has to pass to send LVL2 trigger
c5 29 downtto 28 not used
Line: 30 to 30
 

Address range from 0x80 to 0xBF is for read only registers above 0xc0 is for read/write registers.
Added:
>
>
APV signal is on ADO_LV 52(positive) and 53(negative)
Timieng trigger: ADO_LV 54(p) 55(n)
lvl1 busy ADO_LV 56(p) 57(n)
lvl2 busy ADO_LV 58(p) 59(n)
 

How to start readout on CTS with old no DMA readout

You need following files (all on lxhadesdaq):
/var/diskless/etrax_fs/develop_board/hades_trb_cts.stapl
Line: 44 to 49
  rw_trbv2 w 0 c5 value->look_up ↑ #values are hex numbers
rw_trbv2 w 0 c6 value->look_up ↑ #values are hex numbers
readout_nodma_trbv2_for_beam -w 10000 -o UDP:$eb_ip:$port &
Added:
>
>

The data is send to the given ip address (eventbuilder).
To collect data it is needed to strart event builder e.g.:
daq_evtbuild -m 1 -d file|null -o ~/test_hld/ -x te -I 1 --ebnum 1 -q 32000000 -S marek
and netmem:
daq_netmem -m 1 -q 3000000 -i UDP:0.0.0.0:$port
 

How to start readout on CTS with DMA readout - this version is close to submit but not usable now !

Ensure You have new kernel: run command dmesg you should get on output "readoutdma v1.0".
If you have this version or higher then run following commands :
Revision 4
23 Jul 2009 - Main.MichaelBoehmer
Line: 1 to 1
 
META TOPICPARENT name="TriggerDistribution"

Status and control registers

Line: 39 to 39
 

To start you have to login on etrax and run following commands:
killall readout_nodma_trbv2_for_beam
Changed:
<
<
jam_trbv2 -aRUN_XILINX_PROC /home/hadaq/develop_board/hades_trb_cts.stapl
>
>
jam_trbv2 --trb -aRUN_XILINX_PROC /home/hadaq/develop_board/hades_trb_cts.stapl
  export DAQ_SETUP=trb60
rw_trbv2 w 0 c5 value->look_up ↑ #values are hex numbers
rw_trbv2 w 0 c6 value->look_up ↑ #values are hex numbers
Revision 3
21 Jul 2009 - Main.MarekPalka
Line: 1 to 1
 
META TOPICPARENT name="TriggerDistribution"

Status and control registers

Line: 24 to 24
 
c5 29 downtto 28 not used
c5 30 enable connection to vulom
c5 31 make double APV pulse
Changed:
<
<
c6
>
>
c6 7 downto 0 LVL2 downscale
 
c6 27 downto 8 frequency of self triggering : 50MHz/value
c6 31 downto 28 length of timing trigger : 100ns + value*10ns
Deleted:
<
<
c6 7 downto 0 LVL2 downscale
 
Changed:
<
<
Above 0xBF registers are read/write below this address only for reading.
>
>
Address range from 0x80 to 0xBF is for read only registers above 0xc0 is for read/write registers.

How to start readout on CTS with old no DMA readout

You need following files (all on lxhadesdaq):
/var/diskless/etrax_fs/develop_board/hades_trb_cts.stapl
/var/diskless/etrax_fs/bin/jam_trbv2
/var/diskless/etrax_fs/bin/rw_trbv2
/var/diskless/etrax_fs/bin/readout_nodma_trbv2_for_beam

To start you have to login on etrax and run following commands:
killall readout_nodma_trbv2_for_beam
jam_trbv2 -aRUN_XILINX_PROC /home/hadaq/develop_board/hades_trb_cts.stapl
export DAQ_SETUP=trb60
rw_trbv2 w 0 c5 value->look_up ↑ #values are hex numbers
rw_trbv2 w 0 c6 value->look_up ↑ #values are hex numbers
readout_nodma_trbv2_for_beam -w 10000 -o UDP:$eb_ip:$port &

How to start readout on CTS with DMA readout - this version is close to submit but not usable now !

Ensure You have new kernel: run command dmesg you should get on output "readoutdma v1.0".
If you have this version or higher then run following commands :
/home/hadaq/jam_trbv2 --trb -aRUN_XILINX_PROC /home/hadaq/designa_name_for_subsystem.stapl
./rw_portB r
./rw_portC r
echo "IOP PROGRAMMING"; insmod /home/hadaq/readoutdma_module10.ko
sleep 1
mm
sleep 1
./readout_dma -w 10000 -o UDP:192.168.0.1:2212 &
sleep 4
echo "FPGA STARTING";
./rw_trbv2 w 0 c2 80000000
./rw_trbv2 w 0 c0 100
./rw_trbv2 w 0 c4 0x35b
./rw_trbv2 w 0 c3 70000002
checkRate.sh

In case of bugs, problems, questions contact with Marek : m.palka@gsi.de smile
 
Deleted:
<
<

How to start readout on CTS

 

-- MarekPalka - 20 Jul 2009
Revision 2
20 Jul 2009 - Main.MarekPalka
Line: 1 to 1
 
META TOPICPARENT name="TriggerDistribution"
Changed:
<
<
++--- Status and control registers
>
>

Status and control registers

 

Address Bit range Meaning
91 15 downto 0 lvl1 trigger tag
Line: 30 to 30
 
c6 7 downto 0 LVL2 downscale

Above 0xBF registers are read/write below this address only for reading.
Added:
>
>

How to start readout on CTS

  -- MarekPalka - 20 Jul 2009
 
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