Difference: TDCReadoutBoardV2 (1 vs. 60)

Revision 60
Changes from r58 to r60
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META TOPICPARENT name="TDCReadoutBoard"
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CBM-RICH

 

Pinout Files of FPGAs

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META FILEATTACHMENT attr="" comment="Shower_Analog2" date="1279537862" name="shower_analog2.pdf" path="shower_analog2.pdf" size="421399" user="MarcinKajetanowicz" version="1.1"
META FILEATTACHMENT attr="" comment="TRB3 Multi Test AddOn1" date="1329480376" name="multitestaddon1_SCM.pdf" path="multitestaddon1_SCM.pdf" size="111490" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="TRB3 schematics" date="1334348277" name="trbv3_SCHEMATIC_michael.pdf" path="trbv3_SCHEMATIC_michael.pdf" size="1039109" user="MichaelTraxler" version="1.1"
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META FILEATTACHMENT attr="" comment="CBM-RICH-FEE" date="1335175515" name="cmb_rich_fee1-alles.pdf" path="cmb_rich_fee1-alles.pdf" size="1273907" user="MichaelTraxler" version="1.1"
 
META FILEATTACHMENT attr="" comment="All documentation" date="1335175903" name="MultiTestAddon1_alles.pdf" path="MultiTestAddon1_alles.pdf" size="945837" user="MichaelTraxler" version="1.1"
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META FILEATTACHMENT attr="" comment="Padiwa1" date="1347228758" name="WASA1-alles.pdf" path="WASA1-alles.pdf" size="804740" user="MichaelTraxler" version="1.1"
Revision 58
Changes from r56 to r58
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META TOPICPARENT name="TDCReadoutBoard"
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TRB Test AddOns

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CTS

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CBM-RICH

 

Pinout Files of FPGAs

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META FILEATTACHMENT attr="" comment="CTS AddOn1 Schematics" date="1277223833" name="CTS_AddOn1-SCM.pdf" path="CTS_AddOn1-SCM.pdf" size="512855" user="JanMichel" version="1.1"
META FILEATTACHMENT attr="" comment="Shower_Analog2" date="1279537862" name="shower_analog2.pdf" path="shower_analog2.pdf" size="421399" user="MarcinKajetanowicz" version="1.1"
META FILEATTACHMENT attr="" comment="TRB3 Multi Test AddOn1" date="1329480376" name="multitestaddon1_SCM.pdf" path="multitestaddon1_SCM.pdf" size="111490" user="MichaelTraxler" version="1.1"
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META FILEATTACHMENT attr="" comment="TRB3 schematics" date="1334348277" name="trbv3_SCHEMATIC_michael.pdf" path="trbv3_SCHEMATIC_michael.pdf" size="1039109" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="CBM-RICH-FEE" date="1335175515" name="cmb_rich_fee1-alles.pdf" path="cmb_rich_fee1-alles.pdf" size="1273907" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="All documentation" date="1335175903" name="MultiTestAddon1_alles.pdf" path="MultiTestAddon1_alles.pdf" size="945837" user="MichaelTraxler" version="1.1"
Revision 56
Changes from r54 to r56
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META TOPICPARENT name="TDCReadoutBoard"
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TRB Test AddOns

 

CTS

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MDC

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META FILEATTACHMENT attr="" comment="Shower AddOn 2" date="1265114922" name="shower-addon2-SCM.pdf" path="shower-addon2-SCM.pdf" size="688031" user="JanMichel" version="1.1"
META FILEATTACHMENT attr="" comment="MDC Concentrator Board v2" date="1268064204" name="MDC_Optical_AddOn2-SCM.pdf" path="MDC_Optical_AddOn2-SCM.pdf" size="520463" user="JanMichel" version="1.1"
META FILEATTACHMENT attr="" comment="CTS AddOn1 Schematics" date="1277223833" name="CTS_AddOn1-SCM.pdf" path="CTS_AddOn1-SCM.pdf" size="512855" user="JanMichel" version="1.1"
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META FILEATTACHMENT attr="" comment="Shower_Analog2" date="1279537862" name="shower_analog2.pdf" path="shower_analog2.pdf" size="421399" user="MarcinKajetanowicz" version="1.1"
META FILEATTACHMENT attr="" comment="TRB3 Multi Test AddOn1" date="1329480376" name="multitestaddon1_SCM.pdf" path="multitestaddon1_SCM.pdf" size="111490" user="MichaelTraxler" version="1.1"
Revision 54
Changes from r52 to r54
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META TOPICPARENT name="TDCReadoutBoard"
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AddOns and other boards

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CTS

 
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TOF

 
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MDC

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META FILEATTACHMENT attr="" comment="RICH ADCM v3" date="1256559419" name="RICH_ADCMv3.pdf" path="RICH_ADCMv3.pdf" size="1948290" user="JanMichel" version="1.1"
META FILEATTACHMENT attr="" comment="MDC Fan-PW3" date="1260267628" name="fan-pw3.pdf" path="fan-pw3.pdf" size="628732" user="JanMichel" version="1.1"
META FILEATTACHMENT attr="" comment="Shower AddOn 2" date="1265114922" name="shower-addon2-SCM.pdf" path="shower-addon2-SCM.pdf" size="688031" user="JanMichel" version="1.1"
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META FILEATTACHMENT attr="" comment="MDC Concentrator Board v2" date="1268064204" name="MDC_Optical_AddOn2-SCM.pdf" path="MDC_Optical_AddOn2-SCM.pdf" size="520463" user="JanMichel" version="1.1"
META FILEATTACHMENT attr="" comment="CTS AddOn1 Schematics" date="1277223833" name="CTS_AddOn1-SCM.pdf" path="CTS_AddOn1-SCM.pdf" size="512855" user="JanMichel" version="1.1"
Revision 52
Changes from r50 to r52
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META TOPICPARENT name="TDCReadoutBoard"
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AddOns and other boards

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Hub

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Shower

 

MDC

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RICH

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Pinout Files of FPGAs

Main Source with latest files: cvs /trbnet/pinout
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META FILEATTACHMENT attr="h" comment="filter" date="1152530505" name="filter.png" path="filter.png" size="39228" user="IngoFroehlich" version="1.1"
META FILEATTACHMENT attr="" comment="Schematics of HadesTRBv2 with bugs" date="1166521530" name="hadestrb2.pdf" path="hadestrb2.pdf" size="796465" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="Corrected schematic" date="1166606586" name="hadestrb2_19122006.pdf" path="C:\OrCAD\OrCAD_10.5\projects\HPTDCV2\hadestrb2_19122006.pdf" size="796252" user="MarcinKajetanowicz" version="1.1"
Line: 140 to 129
 
META FILEATTACHMENT attr="" comment="Schematics of FAN_PW2" date="1249932387" name="MDC-FAN-LW2-SCM.pdf" path="MDC-FAN-LW2-SCM.pdf" size="514361" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="Schematics of MDC OEP3" date="1250280559" name="MDC_OEP3-SCM3.pdf" path="MDC_OEP3-SCM3.pdf" size="117586" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="RICH ADCM v3" date="1256559419" name="RICH_ADCMv3.pdf" path="RICH_ADCMv3.pdf" size="1948290" user="JanMichel" version="1.1"
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META FILEATTACHMENT attr="" comment="MDC Fan-PW3" date="1260267628" name="fan-pw3.pdf" path="fan-pw3.pdf" size="628732" user="JanMichel" version="1.1"
META FILEATTACHMENT attr="" comment="Shower AddOn 2" date="1265114922" name="shower-addon2-SCM.pdf" path="shower-addon2-SCM.pdf" size="688031" user="JanMichel" version="1.1"
Revision 50
Changes from r48 to r50
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META TOPICPARENT name="TDCReadoutBoard"
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TRBv2b How To

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TRBv2 How To

 
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Things we learned from ETRAX_FS_DEV1

  1. A Ceramic Capacitor (100V) on 48V is missing (100nF).
  2. Take care of the LEDs. They are not correct on the ETRAX_FS_DEV1
  3. The ispPower-device has to be on a seperate JTAG chain, because the chain will be disrupted when the isp-Power-Chip turns off the power of the ETRAX-FS, which is in the same chain! Not true, the ispPower has the TDISELECT-pin to chose a different TDI pin. everything is perfectly correct in the ETRAX_FS_DEV1 as long as the ispPower is the last device in the JTAG-chain.
  4. The stupid Xilinx-Impact software doesn't allow to program "alien" parts (I (MT) had a conversation with Lattice and Xilinx Engineers). So, we are forced to use a Lattice cable for the clock and power chip. I already ordered a cable (2006-06-28). Then we should forsee on the TRBV2 a simple standard pin-header with the clock and power chips from lattice in this chain.
  5. The ispClock chip should have a pi-filter with ferrite bead at least on the AVDD-pins (e.g. BLM18BA050SN1B)
  6. The schematics should contain in very big letters the purpose of the sheet, like "CLOCK". (see IPU_LINK: connector)
  7. The KW010A needs the remote pin to be pulled down, so J8 should have a 0Ohm to GND.
  8. please use decriptive but short (less than 8 characters with number) names on the part designators where applicable.
  9. If possible, most of the nets should have names to avoid searching for N134234231 on the layout..
  10. The TLK2501 needs a 10uF cap at VCC_R.
  11. It would be nice to have the reference clock shifted by 25ps from each TDC to the next, to have a better time resolution.
  12. Power LEDs are only working down to 2.5V (also barely working). 5 LEDs are really to much! So, one LED for 5V and one LED from the ispPowerChip is enough, which would be an and of all voltages.
  13. The Jumper for BS6 of the EtraxFS should be set to 16-bit flash and not 32-bit flash

Errors found in the version 2 design

TRBv2A

see TDCReadoutBoardV2Errors

TRBv2B

TDCReadoutBoardV2bErrors
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Errors found in previous design versions

 
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TRBv2C

TDCReadoutBoardV2cErrors
 
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Errors found on AddOns

List of Errors on AddOns: TrbAddOnErrors
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Components

 
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Components

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Connector to Add-On.

 
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Connector to Add-On.

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see TDCReadoutBoardV2AddOn

Connector to Motherboard.

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Connector to Motherboard.

 

2006-05-30
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80 TEST2 /
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TigerSHARC

PIN Number of CMOS-PINs Comments PINs connected to Virtex4
SCLKRAT 3 PLL muliplier, can be hardwired to 000 at 125MHz 0
SCLK 1 to lattice clock driver, 125MHz, if less, change SCLKRAT 0
RST_IN 1 Virtex should reset the DSP 1
RST_OUT 1 conn. to POR_IN  
    conn. in addition to Vitrex 1
POR_IN 1 conn. to RST_OUT 0
ADDR 32 conn. to Virtex 32
DATA0-31 32 conn. to Virtex 32
DATA32-63 32 NC 0
RD, WRL, WRH 3 conn. to VIRTEX in any case 3
ACK 1 conn. to VIRTEX in any case 1
BMS 1 Output after reset, but input during reset, selects boot via LP/Host, very important!!! 1
    otherwise the DSP tries to boot via EEPROM  
MS 2 unconnected, no external memory 0
MSH 1 conn to Virtex, access to host maybe usefull? 0
BRST 1 to VIRTEX 1
BR0 1 output, since DSP000, -> NC 0
BR1-7 7 pulled up to VDD_IO via Resistor 0
ID0-2 3 unconnected, has internal pull down 0
BM 1 NC 0
BOFF 1 to VIRTEX 1
BUSLOCK 1 to VIRTEX 1
HBR, HBG 2 to VIRTEX, important! 2
CPA 1 not needed, leave unconnected 0
DPA 1 not needed, leave unconnected 0
DMAR0-3 4 to VIRTEX 4
IOWR, IORD, IOEN 3 to VIRTEX 3
MSSD0-3 4 not needed, leave unconnected 0
RAS, CAS, LDQM 3 not needed, leave unconnected 0
SDA10, SDCKE, SDWE 3 not needed, leave unconnected 0
EMU 1 JTAG needed? 0
TCK 1 JTAG 0
TDI 1 JTAG 0
TDO 1 JTAG 0
TMS 1 JTAG important to pull down during powerup !!! (famous TIP bug) 0
TRST 1 JTAG 0
FLAG0-3 4 to VIRTEX 4
IRQ0-3 4 to VIRTEX 4
TMROE 1 Output: Timer, most likely not needed 1
    During Reset: Input, must be HIGH at Reset (otherwise LP one 1bit  
LxACKI 4 Link Port 4
LxBCMPO 4 Link Port for DMA 4
LxACKO 4 LP 4
LxBCMPI 4 LP 4
CONTROLIMP0,1 2 Needs Pull-down 0
DS0-2 3 should match board imepdance -> Question to board layouter, Imp goes from 26Ohm->120Ohm 0
ENEDREG 1 connect to VSS 0
Total to XILINX     108

PIN Number of LVDS-PAIRs Comments PINs connected to Virtex4
LxDATO0-3 12   24
LxCLKOUT 4   8
LxDATI0-3 12 if not conn -> pull up to VDD_IO 24
LxCLKIN0-3 4 if not conn -> pull up to VDD_IO 8
Total to XILINX     64

Unclear: How many link-ports do we need? At least 2, maybe all 4?

Power Pins:

  • VDD 1.05V for 500MHz, 1.20V for 600MHz
  • VDD_A (for the PLL, very important to make a good decoupling!!!) same value as VDD
  • VDD_IO 2.5V
  • VDD_DRAM 1.5V for 500MHz, 1.6V for 600MHz

filter

ALERT! There is a nice app note from XILIX: (XAPP727) with PCB design rules for connecting the TS20x LP to a Virtex4: http://direct.xilinx.com/bvdocs/appnotes/xapp727.pdf This link is not easily available, therefore I uploaded the xapp727 in our wiki. (Michael)
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TigerSHARC

 
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Optical Link

 
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There is another nice documentation how to replace the TLKxxx by the RocketIO of a XILINX2/4: http://direct.xilinx.com/bvdocs/whitepapers/wp160.pdf
 

Schematics, Pinout and Patches of our PCBs, TRB and the AddOns

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  A list of Patches on the boards can be found here: TrbPatches

TRB

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  • hadestrb2b.pdf: Corrected schematic Still found the following error: The add-on connector should be: QTE-040-02 (larger distance between TRB and add-on, no impact for the user!)
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AddOns

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AddOns and other boards

 
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RICH hardware

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Hub

 
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MDC

 
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MDC hardware

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RICH

 
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Pinout Files of FPGAs

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Main Source with latest files: cvs /trbnet/pinout
 

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META FILEATTACHMENT attr="" comment="Application note from Xilinx" date="1151090861" name="xapp727.zip" path="xapp727.zip" size="838531" user="MichaelTraxler" version="1.1"
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META FILEATTACHMENT attr="h" comment="filter" date="1152530505" name="filter.png" path="filter.png" size="39228" user="IngoFroehlich" version="1.1"
META FILEATTACHMENT attr="" comment="Schematics of HadesTRBv2 with bugs" date="1166521530" name="hadestrb2.pdf" path="hadestrb2.pdf" size="796465" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="Corrected schematic" date="1166606586" name="hadestrb2_19122006.pdf" path="C:\OrCAD\OrCAD_10.5\projects\HPTDCV2\hadestrb2_19122006.pdf" size="796252" user="MarcinKajetanowicz" version="1.1"
Line: 267 to 139
 
META FILEATTACHMENT attr="" comment="ADCMv1 schematic" date="1245410569" name="ETNA_015_best_r4.pdf" path="ETNA_015_best_r4.pdf" size="1368350" user="MichaelBoehmer" version="1.1"
META FILEATTACHMENT attr="" comment="Schematics of FAN_PW2" date="1249932387" name="MDC-FAN-LW2-SCM.pdf" path="MDC-FAN-LW2-SCM.pdf" size="514361" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="Schematics of MDC OEP3" date="1250280559" name="MDC_OEP3-SCM3.pdf" path="MDC_OEP3-SCM3.pdf" size="117586" user="MichaelTraxler" version="1.1"
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META FILEATTACHMENT attr="" comment="RICH ADCM v3" date="1256559419" name="RICH_ADCMv3.pdf" path="RICH_ADCMv3.pdf" size="1948290" user="JanMichel" version="1.1"
Revision 48
Changes from r46 to r48
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META TOPICPARENT name="TDCReadoutBoard"
Line: 203 to 203
 

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MDC hardware

 

Pinout Files of FPGAs

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META FILEATTACHMENT attr="" comment="MDC_DC_LWL1: pinout" date="1229333310" name="mdc_dc_lvl1.lpf" path="mdc_dc_lvl1.lpf" size="3985" user="AttilioTarantola" version="1.3"
META FILEATTACHMENT attr="h" comment="OPTICAL_END_POINT_V2: pinout" date="1229333440" name="mdc_dc_lvl2.lpf" path="mdc_dc_lvl2.lpf" size="4234" user="AttilioTarantola" version="1.1"
META FILEATTACHMENT attr="" comment="HADES TRB HUB2 Schematics" date="1232970069" name="TRB-HUB2-SCM.pdf" path="TRB-HUB2-SCM.pdf" size="529889" user="MichaelTraxler" version="1.1"
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META FILEATTACHMENT attr="" comment="MDC OEP3 Schematics" date="1232970158" name="MDC_OEP3-SCM3.pdf" path="MDC_OEP3-SCM3.pdf" size="117586" user="MichaelTraxler" version="1.1"
 
META FILEATTACHMENT attr="" comment="Shower Interface Board" date="1232976043" name="Shower-Inter1-SCM.pdf" path="Shower-Inter1-SCM.pdf" size="123933" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="Schematics of TOF-AddOn2a" date="1236428422" name="HadesTRB_TOF_ADDON2a-SCM.pdf" path="HadesTRB_TOF_ADDON2a-SCM.pdf" size="1178746" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="MDC_DC_LWL2: pinout" date="1237670418" name="mdc_oepb_v2.lpf" path="mdc_oepb_v2.lpf" size="3545" user="JanMichel" version="1.1"
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META FILEATTACHMENT attr="" comment="Hubv2 FPGA2 pinout" date="1237820882" name="TRB_HUB2_FPGA2.lpf" path="TRB_HUB2_FPGA2.lpf" size="16976" user="JanMichel" version="1.1"
META FILEATTACHMENT attr="" comment="RICH ADCMv2" date="1245410376" name="ETNA_8L_final_D.pdf" path="ETNA_8L_final_D.pdf" size="1910089" user="MichaelBoehmer" version="1.1"
META FILEATTACHMENT attr="" comment="ADCMv1 schematic" date="1245410569" name="ETNA_015_best_r4.pdf" path="ETNA_015_best_r4.pdf" size="1368350" user="MichaelBoehmer" version="1.1"
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META FILEATTACHMENT attr="" comment="Schematics of FAN_PW2" date="1249932387" name="MDC-FAN-LW2-SCM.pdf" path="MDC-FAN-LW2-SCM.pdf" size="514361" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="Schematics of MDC OEP3" date="1250280559" name="MDC_OEP3-SCM3.pdf" path="MDC_OEP3-SCM3.pdf" size="117586" user="MichaelTraxler" version="1.1"
Revision 46
Changes from r44 to r46
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META TOPICPARENT name="TDCReadoutBoard"
Line: 39 to 39
 

TRBv2C

TDCReadoutBoardV2cErrors
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Errors found in the TRB-MDC-Optical-AddOn1 design

  1. The silk-screen (text on the PCB) of the LEDs are not corresponding to the FOT number. So, e.g. FOT13 has a LED with the text RX5 or so.
  2. The connections between the two FPGAs are not ideal, as some of the buses are crossing banks, which makes big problems with the timing of parallel buses. As the split has to be done it could at least be the same at both FPGAs.
  3. The temperature sensor should be connected also to the FPGA, not only to the Etrax. (workaround: Connect JT32 to via of R174 (side facing to fpga1) - not perfect due to 2.5V port-IO voltage, but seems to work)
  4. C9 is switched in polarity.
  5. The ref-clock inputs need 1.8V CML input levels, so they need SI531KA100M. (the current design has SI531FA100M000).
  6. The ECP2M20 needs a 125MHz clock, not a 100MHz, and additionally it has to be a "KA" (1.8V CML). Anyway, we should keep the 100MHz frequencies going to the FPGA, as this is a fundamental frequency of many users.
  7. The Pins of the 48V DCDC converter are quite long - risk of shorts when connected to a TRB even with distance pieces.
  8. FPGA3 has no dedicated reset signal from Power Manager
  9. There is no dedicated clock connection between FPGA1/2 and FPGA3(FCLK is used as common clock for all fpgas)
  10. FPGA1 has no dedicated reset signal from Power Manager
  11. FPGA2 / Serdes LLC0 (TX/RX1): RX and TX are interchanged!
  12. SFP are missing pull-resistors
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Errors found on AddOns

List of Errors on AddOns: TrbAddOnErrors
 

Components

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RICH hardware

 

Pinout Files of FPGAs

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META FILEATTACHMENT attr="" comment="MDC_DC_LWL2: pinout" date="1237670418" name="mdc_oepb_v2.lpf" path="mdc_oepb_v2.lpf" size="3545" user="JanMichel" version="1.1"
META FILEATTACHMENT attr="" comment="Hubv2 FPGA1 pinout" date="1237820867" name="TRB_HUB2_FPGA1.lpf" path="TRB_HUB2_FPGA1.lpf" size="18871" user="JanMichel" version="1.1"
META FILEATTACHMENT attr="" comment="Hubv2 FPGA2 pinout" date="1237820882" name="TRB_HUB2_FPGA2.lpf" path="TRB_HUB2_FPGA2.lpf" size="16976" user="JanMichel" version="1.1"
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META FILEATTACHMENT attr="" comment="RICH ADCMv2" date="1245410376" name="ETNA_8L_final_D.pdf" path="ETNA_8L_final_D.pdf" size="1910089" user="MichaelBoehmer" version="1.1"
META FILEATTACHMENT attr="" comment="ADCMv1 schematic" date="1245410569" name="ETNA_015_best_r4.pdf" path="ETNA_015_best_r4.pdf" size="1368350" user="MichaelBoehmer" version="1.1"
Revision 44
Changes from r42 to r44
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"
Line: 170 to 170
  There is another nice documentation how to replace the TLKxxx by the RocketIO of a XILINX2/4: http://direct.xilinx.com/bvdocs/whitepapers/wp160.pdf
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Schematics of our PCBs, TRB and the AddOns

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Schematics, Pinout and Patches of our PCBs, TRB and the AddOns

 
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Patches

A list of Patches on the boards can be found here: TrbPatches
 

TRB

Line: 224 to 226
 

Changed:
<
<
>
>
 
Changed:
<
<
>
>

 

META FILEATTACHMENT attr="" comment="Application note from Xilinx" date="1151090861" name="xapp727.zip" path="xapp727.zip" size="838531" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="h" comment="filter" date="1152530505" name="filter.png" path="filter.png" size="39228" user="IngoFroehlich" version="1.1"
Line: 249 to 255
 
META FILEATTACHMENT attr="" comment="TRB_MDC_OPTICAL_ADDON: FPGA2" date="1227805465" name="mdcopt_fpga2.lpf" path="mdcopt_fpga2.lpf" size="32807" user="JanMichel" version="1.1"
META FILEATTACHMENT attr="" comment="TRB_MDC_OPTICAL_ADDON: FPGA3 Pinout" date="1227805493" name="mdcopt_fpga3.lpf" path="mdcopt_fpga3.lpf" size="10934" user="JanMichel" version="1.1"
META FILEATTACHMENT attr="" comment="Optical Transmission Driver Card version 2" date="1229332850" name="MDC-DC-LWL2-SCM.pdf" path="MDC-DC-LWL2-SCM.pdf" size="96746" user="AttilioTarantola" version="1.1"
Changed:
<
<
META FILEATTACHMENT attr="" comment="OPTICAL_END_POINT_V1: pinout" date="1229333310" name="mdc_dc_lvl1.lpf" path="mdc_dc_lvl1.lpf" size="3985" user="AttilioTarantola" version="1.3"
>
>
META FILEATTACHMENT attr="" comment="MDC_DC_LWL1: pinout" date="1229333310" name="mdc_dc_lvl1.lpf" path="mdc_dc_lvl1.lpf" size="3985" user="AttilioTarantola" version="1.3"
 
META FILEATTACHMENT attr="h" comment="OPTICAL_END_POINT_V2: pinout" date="1229333440" name="mdc_dc_lvl2.lpf" path="mdc_dc_lvl2.lpf" size="4234" user="AttilioTarantola" version="1.1"
META FILEATTACHMENT attr="" comment="HADES TRB HUB2 Schematics" date="1232970069" name="TRB-HUB2-SCM.pdf" path="TRB-HUB2-SCM.pdf" size="529889" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="MDC OEP3 Schematics" date="1232970158" name="MDC_OEP3-SCM3.pdf" path="MDC_OEP3-SCM3.pdf" size="117586" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="Shower Interface Board" date="1232976043" name="Shower-Inter1-SCM.pdf" path="Shower-Inter1-SCM.pdf" size="123933" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="Schematics of TOF-AddOn2a" date="1236428422" name="HadesTRB_TOF_ADDON2a-SCM.pdf" path="HadesTRB_TOF_ADDON2a-SCM.pdf" size="1178746" user="MichaelTraxler" version="1.1"
Changed:
<
<
META FILEATTACHMENT attr="" comment="OPTICAL_END_POINT_V2: pinout" date="1237670418" name="mdc_oepb_v2.lpf" path="mdc_oepb_v2.lpf" size="3545" user="JanMichel" version="1.1"
>
>
META FILEATTACHMENT attr="" comment="MDC_DC_LWL2: pinout" date="1237670418" name="mdc_oepb_v2.lpf" path="mdc_oepb_v2.lpf" size="3545" user="JanMichel" version="1.1"
META FILEATTACHMENT attr="" comment="Hubv2 FPGA1 pinout" date="1237820867" name="TRB_HUB2_FPGA1.lpf" path="TRB_HUB2_FPGA1.lpf" size="18871" user="JanMichel" version="1.1"
META FILEATTACHMENT attr="" comment="Hubv2 FPGA2 pinout" date="1237820882" name="TRB_HUB2_FPGA2.lpf" path="TRB_HUB2_FPGA2.lpf" size="16976" user="JanMichel" version="1.1"
Revision 42
Changes from r40 to r42
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"
Line: 205 to 205
 

Added:
>
>
 

Pinout Files of FPGAs

Line: 222 to 224
 

Deleted:
<
<

 
Changed:
<
<

>
>
 

META FILEATTACHMENT attr="" comment="Application note from Xilinx" date="1151090861" name="xapp727.zip" path="xapp727.zip" size="838531" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="h" comment="filter" date="1152530505" name="filter.png" path="filter.png" size="39228" user="IngoFroehlich" version="1.1"
Line: 255 to 250
 
META FILEATTACHMENT attr="" comment="TRB_MDC_OPTICAL_ADDON: FPGA3 Pinout" date="1227805493" name="mdcopt_fpga3.lpf" path="mdcopt_fpga3.lpf" size="10934" user="JanMichel" version="1.1"
META FILEATTACHMENT attr="" comment="Optical Transmission Driver Card version 2" date="1229332850" name="MDC-DC-LWL2-SCM.pdf" path="MDC-DC-LWL2-SCM.pdf" size="96746" user="AttilioTarantola" version="1.1"
META FILEATTACHMENT attr="" comment="OPTICAL_END_POINT_V1: pinout" date="1229333310" name="mdc_dc_lvl1.lpf" path="mdc_dc_lvl1.lpf" size="3985" user="AttilioTarantola" version="1.3"
Changed:
<
<
META FILEATTACHMENT attr="" comment="OPTICAL_END_POINT_V2: pinout" date="1229333440" name="mdc_dc_lvl2.lpf" path="mdc_dc_lvl2.lpf" size="4234" user="AttilioTarantola" version="1.1"
>
>
META FILEATTACHMENT attr="h" comment="OPTICAL_END_POINT_V2: pinout" date="1229333440" name="mdc_dc_lvl2.lpf" path="mdc_dc_lvl2.lpf" size="4234" user="AttilioTarantola" version="1.1"
 
META FILEATTACHMENT attr="" comment="HADES TRB HUB2 Schematics" date="1232970069" name="TRB-HUB2-SCM.pdf" path="TRB-HUB2-SCM.pdf" size="529889" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="MDC OEP3 Schematics" date="1232970158" name="MDC_OEP3-SCM3.pdf" path="MDC_OEP3-SCM3.pdf" size="117586" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="Shower Interface Board" date="1232976043" name="Shower-Inter1-SCM.pdf" path="Shower-Inter1-SCM.pdf" size="123933" user="MichaelTraxler" version="1.1"
Added:
>
>
META FILEATTACHMENT attr="" comment="Schematics of TOF-AddOn2a" date="1236428422" name="HadesTRB_TOF_ADDON2a-SCM.pdf" path="HadesTRB_TOF_ADDON2a-SCM.pdf" size="1178746" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="OPTICAL_END_POINT_V2: pinout" date="1237670418" name="mdc_oepb_v2.lpf" path="mdc_oepb_v2.lpf" size="3545" user="JanMichel" version="1.1"
Revision 40
Changes from r38 to r40
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"
Line: 43 to 43
 

  1. The silk-screen (text on the PCB) of the LEDs are not corresponding to the FOT number. So, e.g. FOT13 has a LED with the text RX5 or so.
  2. The connections between the two FPGAs are not ideal, as some of the buses are crossing banks, which makes big problems with the timing of parallel buses. As the split has to be done it could at least be the same at both FPGAs.
Changed:
<
<
  1. The temperature sensor should be connected also to the FPGA, not only to the Etrax. (workaround: Connect JT32 to via of R174 (side facing to fpga1))
>
>
  1. The temperature sensor should be connected also to the FPGA, not only to the Etrax. (workaround: Connect JT32 to via of R174 (side facing to fpga1) - not perfect due to 2.5V port-IO voltage, but seems to work)
 
  1. C9 is switched in polarity.
  2. The ref-clock inputs need 1.8V CML input levels, so they need SI531KA100M. (the current design has SI531FA100M000).
  3. The ECP2M20 needs a 125MHz clock, not a 100MHz, and additionally it has to be a "KA" (1.8V CML). Anyway, we should keep the 100MHz frequencies going to the FPGA, as this is a fundamental frequency of many users.
  4. The Pins of the 48V DCDC converter are quite long - risk of shorts when connected to a TRB even with distance pieces.
  5. FPGA3 has no dedicated reset signal from Power Manager
Changed:
<
<
  1. There is no dedicated clock connection between FPGA1/2 and FPGA3 (for synchronous data transfers)
>
>
  1. There is no dedicated clock connection between FPGA1/2 and FPGA3(FCLK is used as common clock for all fpgas)
 
  1. FPGA1 has no dedicated reset signal from Power Manager
  2. FPGA2 / Serdes LLC0 (TX/RX1): RX and TX are interchanged!
Added:
>
>
  1. SFP are missing pull-resistors
 

Components

Revision 38
Changes from r36 to r38
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"
Line: 198 to 198
 

Added:
>
>

 

Pinout Files of FPGAs

Line: 245 to 255
 
META FILEATTACHMENT attr="" comment="Optical Transmission Driver Card version 2" date="1229332850" name="MDC-DC-LWL2-SCM.pdf" path="MDC-DC-LWL2-SCM.pdf" size="96746" user="AttilioTarantola" version="1.1"
META FILEATTACHMENT attr="" comment="OPTICAL_END_POINT_V1: pinout" date="1229333310" name="mdc_dc_lvl1.lpf" path="mdc_dc_lvl1.lpf" size="3985" user="AttilioTarantola" version="1.3"
META FILEATTACHMENT attr="" comment="OPTICAL_END_POINT_V2: pinout" date="1229333440" name="mdc_dc_lvl2.lpf" path="mdc_dc_lvl2.lpf" size="4234" user="AttilioTarantola" version="1.1"
Added:
>
>
META FILEATTACHMENT attr="" comment="HADES TRB HUB2 Schematics" date="1232970069" name="TRB-HUB2-SCM.pdf" path="TRB-HUB2-SCM.pdf" size="529889" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="MDC OEP3 Schematics" date="1232970158" name="MDC_OEP3-SCM3.pdf" path="MDC_OEP3-SCM3.pdf" size="117586" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="Shower Interface Board" date="1232976043" name="Shower-Inter1-SCM.pdf" path="Shower-Inter1-SCM.pdf" size="123933" user="MichaelTraxler" version="1.1"
Revision 36
Changes from r34 to r36
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"
Line: 51 to 51
 
  1. FPGA3 has no dedicated reset signal from Power Manager
  2. There is no dedicated clock connection between FPGA1/2 and FPGA3 (for synchronous data transfers)
  3. FPGA1 has no dedicated reset signal from Power Manager
Added:
>
>
  1. FPGA2 / Serdes LLC0 (TX/RX1): RX and TX are interchanged!
 

Components

Line: 195 to 196
 

Added:
>
>

 

Pinout Files of FPGAs

Line: 211 to 214
 

Added:
>
>

 
META FILEATTACHMENT attr="" comment="Application note from Xilinx" date="1151090861" name="xapp727.zip" path="xapp727.zip" size="838531" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="h" comment="filter" date="1152530505" name="filter.png" path="filter.png" size="39228" user="IngoFroehlich" version="1.1"
META FILEATTACHMENT attr="" comment="Schematics of HadesTRBv2 with bugs" date="1166521530" name="hadestrb2.pdf" path="hadestrb2.pdf" size="796465" user="MichaelTraxler" version="1.1"
Line: 231 to 242
 
META FILEATTACHMENT attr="" comment="TRB_MDC_OPTICAL_ADDON: FPGA1" date="1227805435" name="mdcopt_fpga1.lpf" path="mdcopt_fpga1.lpf" size="33840" user="JanMichel" version="1.1"
META FILEATTACHMENT attr="" comment="TRB_MDC_OPTICAL_ADDON: FPGA2" date="1227805465" name="mdcopt_fpga2.lpf" path="mdcopt_fpga2.lpf" size="32807" user="JanMichel" version="1.1"
META FILEATTACHMENT attr="" comment="TRB_MDC_OPTICAL_ADDON: FPGA3 Pinout" date="1227805493" name="mdcopt_fpga3.lpf" path="mdcopt_fpga3.lpf" size="10934" user="JanMichel" version="1.1"
Added:
>
>
META FILEATTACHMENT attr="" comment="Optical Transmission Driver Card version 2" date="1229332850" name="MDC-DC-LWL2-SCM.pdf" path="MDC-DC-LWL2-SCM.pdf" size="96746" user="AttilioTarantola" version="1.1"
META FILEATTACHMENT attr="" comment="OPTICAL_END_POINT_V1: pinout" date="1229333310" name="mdc_dc_lvl1.lpf" path="mdc_dc_lvl1.lpf" size="3985" user="AttilioTarantola" version="1.3"
META FILEATTACHMENT attr="" comment="OPTICAL_END_POINT_V2: pinout" date="1229333440" name="mdc_dc_lvl2.lpf" path="mdc_dc_lvl2.lpf" size="4234" user="AttilioTarantola" version="1.1"
Revision 34
Changes from r32 to r34
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"
Line: 43 to 43
 

  1. The silk-screen (text on the PCB) of the LEDs are not corresponding to the FOT number. So, e.g. FOT13 has a LED with the text RX5 or so.
  2. The connections between the two FPGAs are not ideal, as some of the buses are crossing banks, which makes big problems with the timing of parallel buses. As the split has to be done it could at least be the same at both FPGAs.
Changed:
<
<
  1. The temperature sensor should be connected also to the FPGA, not only to the Etrax.
>
>
  1. The temperature sensor should be connected also to the FPGA, not only to the Etrax. (workaround: Connect JT32 to via of R174 (side facing to fpga1))
 
  1. C9 is switched in polarity.
  2. The ref-clock inputs need 1.8V CML input levels, so they need SI531KA100M. (the current design has SI531FA100M000).
  3. The ECP2M20 needs a 125MHz clock, not a 100MHz, and additionally it has to be a "KA" (1.8V CML). Anyway, we should keep the 100MHz frequencies going to the FPGA, as this is a fundamental frequency of many users.
  4. The Pins of the 48V DCDC converter are quite long - risk of shorts when connected to a TRB even with distance pieces.
Changed:
<
<
  1. FPGA3 has no dedicated reset signal from Power Manager.
>
>
  1. FPGA3 has no dedicated reset signal from Power Manager
 
  1. There is no dedicated clock connection between FPGA1/2 and FPGA3 (for synchronous data transfers)
Added:
>
>
  1. FPGA1 has no dedicated reset signal from Power Manager
 

Components

Line: 204 to 205
 

Added:
>
>

 
META FILEATTACHMENT attr="" comment="Application note from Xilinx" date="1151090861" name="xapp727.zip" path="xapp727.zip" size="838531" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="h" comment="filter" date="1152530505" name="filter.png" path="filter.png" size="39228" user="IngoFroehlich" version="1.1"
META FILEATTACHMENT attr="" comment="Schematics of HadesTRBv2 with bugs" date="1166521530" name="hadestrb2.pdf" path="hadestrb2.pdf" size="796465" user="MichaelTraxler" version="1.1"
Line: 221 to 228
 
META FILEATTACHMENT attr="" comment="Rich ADCM Pinout" date="1226665447" name="RICHADCM.lpf" path="RICH ADCM.lpf" size="22340" user="JanMichel" version="1.1"
META FILEATTACHMENT attr="" comment="TRB2_B Pinout" date="1226665756" name="trb2.ucf" path="trb2.ucf" size="11415" user="JanMichel" version="1.1"
META FILEATTACHMENT attr="" comment="Rich AddOn / Hub AddOn Pinout" date="1226666112" name="Hub-RICHAddOn.lpf" path="Hub - RICH AddOn.lpf" size="19217" user="JanMichel" version="1.1"
Added:
>
>
META FILEATTACHMENT attr="" comment="TRB_MDC_OPTICAL_ADDON: FPGA1" date="1227805435" name="mdcopt_fpga1.lpf" path="mdcopt_fpga1.lpf" size="33840" user="JanMichel" version="1.1"
META FILEATTACHMENT attr="" comment="TRB_MDC_OPTICAL_ADDON: FPGA2" date="1227805465" name="mdcopt_fpga2.lpf" path="mdcopt_fpga2.lpf" size="32807" user="JanMichel" version="1.1"
META FILEATTACHMENT attr="" comment="TRB_MDC_OPTICAL_ADDON: FPGA3 Pinout" date="1227805493" name="mdcopt_fpga3.lpf" path="mdcopt_fpga3.lpf" size="10934" user="JanMichel" version="1.1"
Revision 32
Changes from r30 to r32
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"
Line: 47 to 47
 
  1. C9 is switched in polarity.
  2. The ref-clock inputs need 1.8V CML input levels, so they need SI531KA100M. (the current design has SI531FA100M000).
  3. The ECP2M20 needs a 125MHz clock, not a 100MHz, and additionally it has to be a "KA" (1.8V CML). Anyway, we should keep the 100MHz frequencies going to the FPGA, as this is a fundamental frequency of many users.
Added:
>
>
  1. The Pins of the 48V DCDC converter are quite long - risk of shorts when connected to a TRB even with distance pieces.
  2. FPGA3 has no dedicated reset signal from Power Manager.
  3. There is no dedicated clock connection between FPGA1/2 and FPGA3 (for synchronous data transfers)
 

Components

Revision 30
Changes from r28 to r30
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"
Line: 39 to 39
 

TRBv2C

TDCReadoutBoardV2cErrors
Added:
>
>

Errors found in the TRB-MDC-Optical-AddOn1 design

  1. The silk-screen (text on the PCB) of the LEDs are not corresponding to the FOT number. So, e.g. FOT13 has a LED with the text RX5 or so.
  2. The connections between the two FPGAs are not ideal, as some of the buses are crossing banks, which makes big problems with the timing of parallel buses. As the split has to be done it could at least be the same at both FPGAs.
  3. The temperature sensor should be connected also to the FPGA, not only to the Etrax.
  4. C9 is switched in polarity.
  5. The ref-clock inputs need 1.8V CML input levels, so they need SI531KA100M. (the current design has SI531FA100M000).
  6. The ECP2M20 needs a 125MHz clock, not a 100MHz, and additionally it has to be a "KA" (1.8V CML). Anyway, we should keep the 100MHz frequencies going to the FPGA, as this is a fundamental frequency of many users.
 

Components

Connector to Add-On.

Line: 182 to 191
 

Added:
>
>

Pinout Files of FPGAs

 
META FILEATTACHMENT attr="" comment="Application note from Xilinx" date="1151090861" name="xapp727.zip" path="xapp727.zip" size="838531" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="h" comment="filter" date="1152530505" name="filter.png" path="filter.png" size="39228" user="IngoFroehlich" version="1.1"
META FILEATTACHMENT attr="" comment="Schematics of HadesTRBv2 with bugs" date="1166521530" name="hadestrb2.pdf" path="hadestrb2.pdf" size="796465" user="MichaelTraxler" version="1.1"
Line: 196 to 215
 
META FILEATTACHMENT attr="" comment="TRBv2 Shower AddOn 1" date="1202219817" name="HADES-SHOWER-ADDON1-SCM.pdf" path="HADES-SHOWER-ADDON1-SCM.pdf" size="938357" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="MDC Optical AddOn with 32 POF Transceivers" date="1215714076" name="TRB-MDC-OPTICAL-ADDON1-SCM.pdf" path="TRB-MDC-OPTICAL-ADDON1-SCM.pdf" size="621315" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="Hadcom dev board ucf" date="1226661266" name="ETRAX_FS_DEV_BOARD.ucf" path="ETRAX_FS_DEV_BOARD.ucf" size="6761" user="JanMichel" version="1.1"
Added:
>
>
META FILEATTACHMENT attr="" comment="Rich ADCM Pinout" date="1226665447" name="RICHADCM.lpf" path="RICH ADCM.lpf" size="22340" user="JanMichel" version="1.1"
META FILEATTACHMENT attr="" comment="TRB2_B Pinout" date="1226665756" name="trb2.ucf" path="trb2.ucf" size="11415" user="JanMichel" version="1.1"
META FILEATTACHMENT attr="" comment="Rich AddOn / Hub AddOn Pinout" date="1226666112" name="Hub-RICHAddOn.lpf" path="Hub - RICH AddOn.lpf" size="19217" user="JanMichel" version="1.1"
Revision 28
Changes from r26 to r28
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"
Line: 180 to 180
 

Added:
>
>
 
META FILEATTACHMENT attr="" comment="Application note from Xilinx" date="1151090861" name="xapp727.zip" path="xapp727.zip" size="838531" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="h" comment="filter" date="1152530505" name="filter.png" path="filter.png" size="39228" user="IngoFroehlich" version="1.1"
META FILEATTACHMENT attr="" comment="Schematics of HadesTRBv2 with bugs" date="1166521530" name="hadestrb2.pdf" path="hadestrb2.pdf" size="796465" user="MichaelTraxler" version="1.1"
Line: 192 to 194
 
META FILEATTACHMENT attr="" comment="MDC-AddOn, with 10 RS485 buses" date="1197897094" name="mdc_addon1-SCM.pdf" path="mdc_addon1-SCM.pdf" size="428577" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="TOF-AddOn, with NINO-chip" date="1197897141" name="HADESTRB_TOF_ADDON1-SCM.pdf" path="HADESTRB_TOF_ADDON1-SCM.pdf" size="675153" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="TRBv2 Shower AddOn 1" date="1202219817" name="HADES-SHOWER-ADDON1-SCM.pdf" path="HADES-SHOWER-ADDON1-SCM.pdf" size="938357" user="MichaelTraxler" version="1.1"
Added:
>
>
META FILEATTACHMENT attr="" comment="MDC Optical AddOn with 32 POF Transceivers" date="1215714076" name="TRB-MDC-OPTICAL-ADDON1-SCM.pdf" path="TRB-MDC-OPTICAL-ADDON1-SCM.pdf" size="621315" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="Hadcom dev board ucf" date="1226661266" name="ETRAX_FS_DEV_BOARD.ucf" path="ETRAX_FS_DEV_BOARD.ucf" size="6761" user="JanMichel" version="1.1"
Revision 26
Changes from r24 to r26
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"
Line: 36 to 36
 

TRBv2B

TDCReadoutBoardV2bErrors
Added:
>
>

TRBv2C

TDCReadoutBoardV2cErrors
 

Components

Connector to Add-On.

Line: 175 to 178
 

Added:
>
>
 
META FILEATTACHMENT attr="" comment="Application note from Xilinx" date="1151090861" name="xapp727.zip" path="xapp727.zip" size="838531" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="h" comment="filter" date="1152530505" name="filter.png" path="filter.png" size="39228" user="IngoFroehlich" version="1.1"
META FILEATTACHMENT attr="" comment="Schematics of HadesTRBv2 with bugs" date="1166521530" name="hadestrb2.pdf" path="hadestrb2.pdf" size="796465" user="MichaelTraxler" version="1.1"
Line: 186 to 191
 
META FILEATTACHMENT attr="" comment="Optical Transmission Driver Card" date="1197896883" name="mdc-dc-lwl1-SCM.pdf" path="mdc-dc-lwl1-SCM.pdf" size="86702" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="MDC-AddOn, with 10 RS485 buses" date="1197897094" name="mdc_addon1-SCM.pdf" path="mdc_addon1-SCM.pdf" size="428577" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="TOF-AddOn, with NINO-chip" date="1197897141" name="HADESTRB_TOF_ADDON1-SCM.pdf" path="HADESTRB_TOF_ADDON1-SCM.pdf" size="675153" user="MichaelTraxler" version="1.1"
Added:
>
>
META FILEATTACHMENT attr="" comment="TRBv2 Shower AddOn 1" date="1202219817" name="HADES-SHOWER-ADDON1-SCM.pdf" path="HADES-SHOWER-ADDON1-SCM.pdf" size="938357" user="MichaelTraxler" version="1.1"
Revision 24
Changes from r22 to r24
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"
Added:
>
>

 

TRBv2b How To

Line: 149 to 152
  There is another nice documentation how to replace the TLKxxx by the RocketIO of a XILINX2/4: http://direct.xilinx.com/bvdocs/whitepapers/wp160.pdf
Changed:
<
<

Schematics of our PCBs

>
>

Schematics of our PCBs, TRB and the AddOns

 
Changed:
<
<
>
>

TRB

 

  • hadestrb2b.pdf: Corrected schematic Still found the following error: The add-on connector should be: QTE-040-02 (larger distance between TRB and add-on, no impact for the user!)
Added:
>
>
 
Added:
>
>

AddOns

 

Changed:
<
<

>
>

 

META FILEATTACHMENT attr="" comment="Application note from Xilinx" date="1151090861" name="xapp727.zip" path="xapp727.zip" size="838531" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="h" comment="filter" date="1152530505" name="filter.png" path="filter.png" size="39228" user="IngoFroehlich" version="1.1"
Line: 170 to 182
 
META FILEATTACHMENT attr="" comment="Corrected schematic" date="1174553755" name="hadestrb2b.pdf" path="hadestrb2b.pdf" size="756678" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="Schematics of TRBv2-General_Purpose_AddOn" date="1181042143" name="GP-ADD_ON1-SCM.pdf" path="GP-ADD_ON1-SCM.pdf" size="178651" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="Schematics of TRBv2-HUB_AddOn" date="1181042199" name="TRB_HUB1-SCM.pdf" path="TRB_HUB1-SCM.pdf" size="365497" user="MichaelTraxler" version="1.1"
Added:
>
>
META FILEATTACHMENT attr="" comment="Schematics of HADESTRBv2c" date="1195492154" name="hadestrb2c.pdf" path="hadestrb2c.pdf" size="790935" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="Optical Transmission Driver Card" date="1197896883" name="mdc-dc-lwl1-SCM.pdf" path="mdc-dc-lwl1-SCM.pdf" size="86702" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="MDC-AddOn, with 10 RS485 buses" date="1197897094" name="mdc_addon1-SCM.pdf" path="mdc_addon1-SCM.pdf" size="428577" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="TOF-AddOn, with NINO-chip" date="1197897141" name="HADESTRB_TOF_ADDON1-SCM.pdf" path="HADESTRB_TOF_ADDON1-SCM.pdf" size="675153" user="MichaelTraxler" version="1.1"
Revision 22
Changes from r20 to r22
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"
Added:
>
>

TRBv2b How To

 

Things we learned from ETRAX_FS_DEV1

  1. A Ceramic Capacitor (100V) on 48V is missing (100nF).
Line: 158 to 161
 

Changed:
<
<

FPGA registers

description address
etrax interface 0
value
1-IDLE
2-SAVE_ADDRESS_1
3-SAVE_ADDRESS_2
4-SAVE_DATA_1
5-SAVE_DATA_2
6-WAIT FOR DATA
7-SEND_VALID
8-SEND_DATA_1
9-SEND_DATA_2
a-SEND_ZERO

description address
busy & TDC register 1
bits value
31-30 00
29-20 how many words in lvl1 memory
19-16 TDC error D,C,B,A
15-0 lvl1 minus lvl2 triggers

description address
daq, sdram, dsp registers 2
bits value
31-28 0
27 data valid to etrax
26 collecting lvl1 event
25 fast lvl2 busy
24 lvl2 busy
23 sending event to etrax
22 lvl1 memory full
21 lvl1 busy
20-19 trigger register LVL2_ACK: 00b-IDLE, 01b-Wait for busy, 10b-sending valid, 11b-error
18-16 trigger register LVL2_TRIGG: 000b-IDLE, 001b-SEND_LVL2_TRIGG_1, 010b-SEND_LVL2_TRIGG_2
18-16 trigger register LVL2_TRIGG: 011b-WAIT_FOR_ACK, others-ERROR
15-14 trigger register LVL1_ACK: 00b-IDLE, 01b-Wait for busy, 10b-sending valid, 11b-error
13-11 trigger register LVL1_TRIGG: 00b-IDLE, 001b-SEND_LVL1_TRIGG_1, 010b-SEND_LVL1_TRIGG_2
13-11 trigger register LVL1_TRIGG: 011b-SEND_LVL1_TRIGG_3, 100b-SEND_LVL1_TRIGG_4
13-11 trigger register LVL1_TRIGG: 101b-WAIT_FOR_ACK , others-ERROR
10-9 trigger register LVL1_DELAY: 00b-IDLE, 01b-DEALY_1,10b-DELAY_2, otehrs error
8-3 sdram register
2-0 dsp register

description address
lvl & lvl2 3
bits value
31-16 lvl1 counter
15-0 lvl2 counter
>
>

 

META FILEATTACHMENT attr="" comment="Application note from Xilinx" date="1151090861" name="xapp727.zip" path="xapp727.zip" size="838531" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="h" comment="filter" date="1152530505" name="filter.png" path="filter.png" size="39228" user="IngoFroehlich" version="1.1"
Revision 20
Changes from r18 to r20
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

Things we learned from ETRAX_FS_DEV1

Line: 146 to 146
  There is another nice documentation how to replace the TLKxxx by the RocketIO of a XILINX2/4: http://direct.xilinx.com/bvdocs/whitepapers/wp160.pdf
Changed:
<
<
>
>

Schematics of our PCBs

 

Changed:
<
<
Still found the following error: The add-on connector should be: QTE-040-02 (larger distance between TRB and add-on)
>
>
Still found the following error: The add-on connector should be: QTE-040-02 (larger distance between TRB and add-on, no impact for the user!)

FPGA registers

description address
etrax interface 0
value
1-IDLE
2-SAVE_ADDRESS_1
3-SAVE_ADDRESS_2
4-SAVE_DATA_1
5-SAVE_DATA_2
6-WAIT FOR DATA
7-SEND_VALID
8-SEND_DATA_1
9-SEND_DATA_2
a-SEND_ZERO

description address
busy & TDC register 1
bits value
31-30 00
29-20 how many words in lvl1 memory
19-16 TDC error D,C,B,A
15-0 lvl1 minus lvl2 triggers

description address
daq, sdram, dsp registers 2
bits value
31-28 0
27 data valid to etrax
26 collecting lvl1 event
25 fast lvl2 busy
24 lvl2 busy
23 sending event to etrax
22 lvl1 memory full
21 lvl1 busy
20-19 trigger register LVL2_ACK: 00b-IDLE, 01b-Wait for busy, 10b-sending valid, 11b-error
18-16 trigger register LVL2_TRIGG: 000b-IDLE, 001b-SEND_LVL2_TRIGG_1, 010b-SEND_LVL2_TRIGG_2
18-16 trigger register LVL2_TRIGG: 011b-WAIT_FOR_ACK, others-ERROR
15-14 trigger register LVL1_ACK: 00b-IDLE, 01b-Wait for busy, 10b-sending valid, 11b-error
13-11 trigger register LVL1_TRIGG: 00b-IDLE, 001b-SEND_LVL1_TRIGG_1, 010b-SEND_LVL1_TRIGG_2
13-11 trigger register LVL1_TRIGG: 011b-SEND_LVL1_TRIGG_3, 100b-SEND_LVL1_TRIGG_4
13-11 trigger register LVL1_TRIGG: 101b-WAIT_FOR_ACK , others-ERROR
10-9 trigger register LVL1_DELAY: 00b-IDLE, 01b-DEALY_1,10b-DELAY_2, otehrs error
8-3 sdram register
2-0 dsp register

description address
lvl & lvl2 3
bits value
31-16 lvl1 counter
15-0 lvl2 counter
 

META FILEATTACHMENT attr="" comment="Application note from Xilinx" date="1151090861" name="xapp727.zip" path="xapp727.zip" size="838531" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="h" comment="filter" date="1152530505" name="filter.png" path="filter.png" size="39228" user="IngoFroehlich" version="1.1"
META FILEATTACHMENT attr="" comment="Schematics of HadesTRBv2 with bugs" date="1166521530" name="hadestrb2.pdf" path="hadestrb2.pdf" size="796465" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="Corrected schematic" date="1166606586" name="hadestrb2_19122006.pdf" path="C:\OrCAD\OrCAD_10.5\projects\HPTDCV2\hadestrb2_19122006.pdf" size="796252" user="MarcinKajetanowicz" version="1.1"
META FILEATTACHMENT attr="" comment="Corrected schematic" date="1174553755" name="hadestrb2b.pdf" path="hadestrb2b.pdf" size="756678" user="MichaelTraxler" version="1.1"
Added:
>
>
META FILEATTACHMENT attr="" comment="Schematics of TRBv2-General_Purpose_AddOn" date="1181042143" name="GP-ADD_ON1-SCM.pdf" path="GP-ADD_ON1-SCM.pdf" size="178651" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="Schematics of TRBv2-HUB_AddOn" date="1181042199" name="TRB_HUB1-SCM.pdf" path="TRB_HUB1-SCM.pdf" size="365497" user="MichaelTraxler" version="1.1"
Revision 18
Changes from r16 to r18
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

Things we learned from ETRAX_FS_DEV1

Line: 24 to 24
 

Errors found in the version 2 design

Added:
>
>

TRBv2A

  see TDCReadoutBoardV2Errors
Added:
>
>

TRBv2B

TDCReadoutBoardV2bErrors
 

Components

Connector to Add-On.

Line: 148 to 152
 

Added:
>
>
Still found the following error: The add-on connector should be: QTE-040-02 (larger distance between TRB and add-on)
 

META FILEATTACHMENT attr="" comment="Application note from Xilinx" date="1151090861" name="xapp727.zip" path="xapp727.zip" size="838531" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="h" comment="filter" date="1152530505" name="filter.png" path="filter.png" size="39228" user="IngoFroehlich" version="1.1"
Revision 16
Changes from r14 to r16
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

Things we learned from ETRAX_FS_DEV1

Line: 147 to 147
 

Added:
>
>
 
META FILEATTACHMENT attr="" comment="Application note from Xilinx" date="1151090861" name="xapp727.zip" path="xapp727.zip" size="838531" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="h" comment="filter" date="1152530505" name="filter.png" path="filter.png" size="39228" user="IngoFroehlich" version="1.1"
META FILEATTACHMENT attr="" comment="Schematics of HadesTRBv2 with bugs" date="1166521530" name="hadestrb2.pdf" path="hadestrb2.pdf" size="796465" user="MichaelTraxler" version="1.1"
Added:
>
>
META FILEATTACHMENT attr="" comment="Corrected schematic" date="1166606586" name="hadestrb2_19122006.pdf" path="C:\OrCAD\OrCAD_10.5\projects\HPTDCV2\hadestrb2_19122006.pdf" size="796252" user="MarcinKajetanowicz" version="1.1"
META FILEATTACHMENT attr="" comment="Corrected schematic" date="1174553755" name="hadestrb2b.pdf" path="hadestrb2b.pdf" size="756678" user="MichaelTraxler" version="1.1"
Revision 14
Changes from r12 to r14
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

Things we learned from ETRAX_FS_DEV1

Line: 22 to 22
 
  1. The Jumper for BS6 of the EtraxFS should be set to 16-bit flash and not 32-bit flash
Added:
>
>

Errors found in the version 2 design

see TDCReadoutBoardV2Errors
 

Components

Connector to Add-On.

Line: 141 to 145
 

Added:
>
>
 
META FILEATTACHMENT attr="" comment="Application note from Xilinx" date="1151090861" name="xapp727.zip" path="xapp727.zip" size="838531" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="h" comment="filter" date="1152530505" name="filter.png" path="filter.png" size="39228" user="IngoFroehlich" version="1.1"
Added:
>
>
META FILEATTACHMENT attr="" comment="Schematics of HadesTRBv2 with bugs" date="1166521530" name="hadestrb2.pdf" path="hadestrb2.pdf" size="796465" user="MichaelTraxler" version="1.1"
Revision 12
Changes from r10 to r12
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

Things we learned from ETRAX_FS_DEV1

Line: 7 to 7
 
  1. The ispPower-device has to be on a seperate JTAG chain, because the chain will be disrupted when the isp-Power-Chip turns off the power of the ETRAX-FS, which is in the same chain! Not true, the ispPower has the TDISELECT-pin to chose a different TDI pin. everything is perfectly correct in the ETRAX_FS_DEV1 as long as the ispPower is the last device in the JTAG-chain.
Deleted:
<
<
  1. For the TRBV2 we should use the 20 pin output ispClock-Chip from lattice
 
  1. The stupid Xilinx-Impact software doesn't allow to program "alien" parts (I (MT) had a conversation with Lattice and Xilinx Engineers). So, we are forced to use a Lattice cable for the clock and power chip. I already ordered a cable (2006-06-28). Then we should forsee on the TRBV2 a simple standard pin-header with the clock and power chips from lattice in
Line: 17 to 16
 
  1. The KW010A needs the remote pin to be pulled down, so J8 should have a 0Ohm to GND.
  2. please use decriptive but short (less than 8 characters with number) names on the part designators where applicable.
  3. If possible, most of the nets should have names to avoid searching for N134234231 on the layout..
Added:
>
>
  1. The TLK2501 needs a 10uF cap at VCC_R.
  2. It would be nice to have the reference clock shifted by 25ps from each TDC to the next, to have a better time resolution.
  3. Power LEDs are only working down to 2.5V (also barely working). 5 LEDs are really to much! So, one LED for 5V and one LED from the ispPowerChip is enough, which would be an and of all voltages.
  4. The Jumper for BS6 of the EtraxFS should be set to 16-bit flash and not 32-bit flash
 

Components

Added:
>
>

Connector to Add-On.

see TDCReadoutBoardV2AddOn
 

Connector to Motherboard.

2006-05-30
Revision 10
Changes from r8 to r10
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

Things we learned from ETRAX_FS_DEV1

Line: 6 to 6
 
  1. Take care of the LEDs. They are not correct on the ETRAX_FS_DEV1
  2. The ispPower-device has to be on a seperate JTAG chain, because the chain will be disrupted when the isp-Power-Chip turns off the power of the ETRAX-FS, which is in the same chain!
Changed:
<
<
Not true, the ispPower has the TDISELECT-pin to chose a different TDI pin. everything is perfectly correct in the ETRAX_FS_DEV1.
>
>
Not true, the ispPower has the TDISELECT-pin to chose a different TDI pin. everything is perfectly correct in the ETRAX_FS_DEV1 as long as the ispPower is the last device in the JTAG-chain.
 
  1. For the TRBV2 we should use the 20 pin output ispClock-Chip from lattice
  2. The stupid Xilinx-Impact software doesn't allow to program "alien" parts (I (MT) had a conversation with Lattice and Xilinx Engineers). So, we are forced to use a Lattice cable for the clock and power chip. I already ordered a cable
Line: 51 to 51
 

TigerSHARC

PIN Number of CMOS-PINs Comments PINs connected to Virtex4
Changed:
<
<
SCLKRAT 3 ?? 0
SCLK 1 ?? 0
>
>
SCLKRAT 3 PLL muliplier, can be hardwired to 000 at 125MHz 0
SCLK 1 to lattice clock driver, 125MHz, if less, change SCLKRAT 0
 
RST_IN 1 Virtex should reset the DSP 1
Changed:
<
<
RST_OUT 1 conn. to POR_IN 0
POR_IN 1   0
ADDR 32 maybe part to be connected to global bus? 32
DATA 64 also part to be connected to global bus? 64
>
>
RST_OUT 1 conn. to POR_IN  
    conn. in addition to Vitrex 1
POR_IN 1 conn. to RST_OUT 0
ADDR 32 conn. to Virtex 32
DATA0-31 32 conn. to Virtex 32
DATA32-63 32 NC 0
 
RD, WRL, WRH 3 conn. to VIRTEX in any case 3
ACK 1 conn. to VIRTEX in any case 1
Changed:
<
<
BMS 1 ?? 0
>
>
BMS 1 Output after reset, but input during reset, selects boot via LP/Host, very important!!! 1
    otherwise the DSP tries to boot via EEPROM  
 
MS 2 unconnected, no external memory 0
Changed:
<
<
MSH 1 unconnected, no access to host 0
>
>
MSH 1 conn to Virtex, access to host maybe usefull? 0
 
BRST 1 to VIRTEX 1
Changed:
<
<
BR0 1 output, since DSP000 0
BR1-7 7 pulled to VDD_IO via Resistor 0
>
>
BR0 1 output, since DSP000, -> NC 0
BR1-7 7 pulled up to VDD_IO via Resistor 0
 
ID0-2 3 unconnected, has internal pull down 0
Changed:
<
<
BM 1 ?? 0
>
>
BM 1 NC 0
 
BOFF 1 to VIRTEX 1
BUSLOCK 1 to VIRTEX 1
HBR, HBG 2 to VIRTEX, important! 2
Line: 86 to 89
 
TRST 1 JTAG 0
FLAG0-3 4 to VIRTEX 4
IRQ0-3 4 to VIRTEX 4
Changed:
<
<
TMROE 1 Timer, most likely not needed 0
>
>
TMROE 1 Output: Timer, most likely not needed 1
    During Reset: Input, must be HIGH at Reset (otherwise LP one 1bit  
 
LxACKI 4 Link Port 4
LxBCMPO 4 Link Port for DMA 4
LxACKO 4 LP 4
LxBCMPI 4 LP 4
Changed:
<
<
CONTROLIMP0,1 2 default is AD? 0
DS0-2 3 should match board imepdance 0
>
>
CONTROLIMP0,1 2 Needs Pull-down 0
DS0-2 3 should match board imepdance -> Question to board layouter, Imp goes from 26Ohm->120Ohm 0
 
ENEDREG 1 connect to VSS 0
Total to XILINX     0
Line: 105 to 109
 

Unclear: How many link-ports do we need? At least 2, maybe all 4?
Added:
>
>
Power Pins:

  • VDD 1.05V for 500MHz, 1.20V for 600MHz
  • VDD_A (for the PLL, very important to make a good decoupling!!!) same value as VDD
  • VDD_IO 2.5V
  • VDD_DRAM 1.5V for 500MHz, 1.6V for 600MHz

filter
  ALERT! There is a nice app note from XILIX: (XAPP727) with PCB design rules for connecting the TS20x LP to a Virtex4: http://direct.xilinx.com/bvdocs/appnotes/xapp727.pdf This link is not easily available, therefore I uploaded the xapp727 in our wiki. (Michael)
Line: 117 to 132
  http://direct.xilinx.com/bvdocs/whitepapers/wp160.pdf
Changed:
<
<

>
>
 

META FILEATTACHMENT attr="" comment="Application note from Xilinx" date="1151090861" name="xapp727.zip" path="xapp727.zip" size="838531" user="MichaelTraxler" version="1.1"
Added:
>
>
META FILEATTACHMENT attr="h" comment="filter" date="1152530505" name="filter.png" path="filter.png" size="39228" user="IngoFroehlich" version="1.1"
Revision 8
Changes from r6 to r8
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

Things we learned from ETRAX_FS_DEV1

Line: 6 to 6
 
  1. Take care of the LEDs. They are not correct on the ETRAX_FS_DEV1
  2. The ispPower-device has to be on a seperate JTAG chain, because the chain will be disrupted when the isp-Power-Chip turns off the power of the ETRAX-FS, which is in the same chain!
Added:
>
>
Not true, the ispPower has the TDISELECT-pin to chose a different TDI pin. everything is perfectly correct in the ETRAX_FS_DEV1.
 
  1. For the TRBV2 we should use the 20 pin output ispClock-Chip from lattice
  2. The stupid Xilinx-Impact software doesn't allow to program "alien" parts (I (MT) had a conversation with Lattice and Xilinx Engineers). So, we are forced to use a Lattice cable for the clock and power chip. I already ordered a cable
Line: 39 to 40
 
72 SCK /
73 CS1 (TRB out)
74 CS1 /
Changed:
<
<
75 CS2 (TRB out)
76 CS2 /
>
>
75 TEMP (1-wire bus for temperature sensor)
76 reserved /
 
77 TEST1 (TRB out)
78 TEST1 /
79 TEST2 (TRB out)
Revision 6
Changes from r4 to r6
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"
Added:
>
>

Things we learned from ETRAX_FS_DEV1

  1. A Ceramic Capacitor (100V) on 48V is missing (100nF).
  2. Take care of the LEDs. They are not correct on the ETRAX_FS_DEV1
  3. The ispPower-device has to be on a seperate JTAG chain, because the chain will be disrupted when the isp-Power-Chip turns off the power of the ETRAX-FS, which is in the same chain!
  4. For the TRBV2 we should use the 20 pin output ispClock-Chip from lattice
  5. The stupid Xilinx-Impact software doesn't allow to program "alien" parts (I (MT) had a conversation with Lattice and Xilinx Engineers). So, we are forced to use a Lattice cable for the clock and power chip. I already ordered a cable (2006-06-28). Then we should forsee on the TRBV2 a simple standard pin-header with the clock and power chips from lattice in this chain.
  6. The ispClock chip should have a pi-filter with ferrite bead at least on the AVDD-pins (e.g. BLM18BA050SN1B)
  7. The schematics should contain in very big letters the purpose of the sheet, like "CLOCK". (see IPU_LINK: connector)
  8. The KW010A needs the remote pin to be pulled down, so J8 should have a 0Ohm to GND.
  9. please use decriptive but short (less than 8 characters with number) names on the part designators where applicable.
  10. If possible, most of the nets should have names to avoid searching for N134234231 on the layout..
 

Components

Connector to Motherboard.

Revision 4
Changes from r2 to r4
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

Components

Line: 11 to 11
 
pin function
63 Sig 8D
64 Sig 8D /
Changed:
<
<
65 reserved (LVDS)
66 reserved /
67 SDI
>
>
65 GND
66 GND
67 SDI (TRB in)
 
68 SDI /
Changed:
<
<
69 SDO
>
>
69 SDO (TRB out)
 
70 SDO /
Changed:
<
<
71 SCK
>
>
71 SCK (TRB out)
 
72 SCK /
Changed:
<
<
73 CS1
>
>
73 CS1 (TRB out)
 
74 CS1 /
Changed:
<
<
75 CS2
>
>
75 CS2 (TRB out)
 
76 CS2 /
Changed:
<
<
77 TEST1
>
>
77 TEST1 (TRB out)
 
78 TEST1 /
Changed:
<
<
79 TEST2
>
>
79 TEST2 (TRB out)
 
80 TEST2 /
Line: 88 to 88
 

ALERT! There is a nice app note from XILIX: (XAPP727) with PCB design rules for connecting the TS20x LP to a Virtex4: http://direct.xilinx.com/bvdocs/appnotes/xapp727.pdf
Added:
>
>
This link is not easily available, therefore I uploaded the xapp727 in our wiki. (Michael)
 

Optical Link

Line: 95 to 98
  http://direct.xilinx.com/bvdocs/whitepapers/wp160.pdf
Added:
>
>

 
Changed:
<
<

-- IngoFroehlich - 09 Mar 2006
>
>
META FILEATTACHMENT attr="" comment="Application note from Xilinx" date="1151090861" name="xapp727.zip" path="xapp727.zip" size="838531" user="MichaelTraxler" version="1.1"
Revision 2
30 May 2006 - Main.MichaelTraxler
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"
Changed:
<
<

Componants

>
>

Components

Connector to Motherboard.

2006-05-30

The Daughterboard and Motherboard designer are asking for the following extension of the pin-definition of the TRB->Motherboard connector:

pin function
63 Sig 8D
64 Sig 8D /
65 reserved (LVDS)
66 reserved /
67 SDI
68 SDI /
69 SDO
70 SDO /
71 SCK
72 SCK /
73 CS1
74 CS1 /
75 CS2
76 CS2 /
77 TEST1
78 TEST1 /
79 TEST2
80 TEST2 /
 

TigerSHARC

 
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