Difference: TDCReadoutBoardV3 (1 vs. 26)

Revision 26
24 Jun 2014 - Main.MichaelTraxler
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META TOPICPARENT name="TDCReadoutBoard"

TRBv3

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Schematics and Layout

Changed:
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  • TRBv3_FPGAs.tar.gz: and the wirelist and the .lpf files for the FPGAs (have to be adjusted to be able to use one file for all 4 FPGAs -> Jan):
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  • TRBv3_FPGAs.tar.gz: and the wirelist and the .lpf files for the FPGAs (have to be adjusted to be able to use one file for all 4 FPGAs -> Jan):
 
Line: 43 to 43
 

Available Boards

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Further Documentation

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META FILEATTACHMENT attr="" comment="Padiwa3 schematics and Layout, for PANDA-MCPs" date="1363000885" name="PADIWA3-alles.pdf" path="PADIWA3-alles.pdf" size="1044734" user="MichaelTraxler" version="1.2"
META FILEATTACHMENT attr="" comment="CBM-TOF FEE schematics" date="1365151304" name="CBM-TOF-FEE1-SCM-NEU.pdf" path="CBM-TOF-FEE1-SCM-NEU.pdf" size="96185" user="CahitUgur" version="1.1"
META FILEATTACHMENT attr="" comment="Padiwa2 Schematics, with MMCX connectors" date="1366804044" name="PADIWA2-all.pdf" path="PADIWA2-all.pdf" size="760619" user="MichaelTraxler" version="1.1"
Changed:
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META FILEATTACHMENT attr="" comment="Padiwa3, connector suited for PANDA-MCP (2mm pitch, %_Q_%alternating signals%_Q_% pinout)" date="1366804078" name="PADIWA3-all.pdf" path="PADIWA3-all.pdf" size="1127365" user="MichaelTraxler" version="1.1"
>
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META FILEATTACHMENT attr="" comment="Padiwa3, connector suited for PANDA-MCP (2mm pitch, %22alternating signals%22 pinout)" date="1366804078" name="PADIWA3-all.pdf" path="PADIWA3-all.pdf" size="1127365" user="MichaelTraxler" version="1.1"
 
META FILEATTACHMENT attr="" comment="TRB3 CTS AddOn1" date="1367942902" name="trb3cts_addon1_alles.pdf" path="trb3cts_addon1_alles.pdf" size="658815" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="AddOn Board with 8 NIM and 16 differential connectors" date="1371714987" name="GPIN_AddOn1_alles.pdf" path="GPIN_AddOn1_alles.pdf" size="458828" user="CahitUgur" version="1.1"
META FILEATTACHMENT attr="" comment="PADIWA-AMPS (Padiwa + Charge Measurement) schematics" date="1379327498" name="padiwa-amps1.pdf" path="padiwa-amps1.pdf" size="247826" user="MichaelTraxler" version="1.1"
Revision 25
16 Sep 2013 - Main.MichaelTraxler
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META TOPICPARENT name="TDCReadoutBoard"

TRBv3

Line: 29 to 29
 
Deleted:
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Changed:
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CBM-RICH

Line: 81 to 80
 
META FILEATTACHMENT attr="" comment="Padiwa3, connector suited for PANDA-MCP (2mm pitch, %_Q_%alternating signals%_Q_% pinout)" date="1366804078" name="PADIWA3-all.pdf" path="PADIWA3-all.pdf" size="1127365" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="TRB3 CTS AddOn1" date="1367942902" name="trb3cts_addon1_alles.pdf" path="trb3cts_addon1_alles.pdf" size="658815" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="AddOn Board with 8 NIM and 16 differential connectors" date="1371714987" name="GPIN_AddOn1_alles.pdf" path="GPIN_AddOn1_alles.pdf" size="458828" user="CahitUgur" version="1.1"
Added:
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META FILEATTACHMENT attr="" comment="PADIWA-AMPS (Padiwa + Charge Measurement) schematics" date="1379327498" name="padiwa-amps1.pdf" path="padiwa-amps1.pdf" size="247826" user="MichaelTraxler" version="1.1"
Revision 24
20 Jun 2013 - Main.CahitUgur
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

TRBv3

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Added:
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PADIWA (PANDA-DIRC-WASA)

Line: 77 to 80
 
META FILEATTACHMENT attr="" comment="Padiwa2 Schematics, with MMCX connectors" date="1366804044" name="PADIWA2-all.pdf" path="PADIWA2-all.pdf" size="760619" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="Padiwa3, connector suited for PANDA-MCP (2mm pitch, %_Q_%alternating signals%_Q_% pinout)" date="1366804078" name="PADIWA3-all.pdf" path="PADIWA3-all.pdf" size="1127365" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="TRB3 CTS AddOn1" date="1367942902" name="trb3cts_addon1_alles.pdf" path="trb3cts_addon1_alles.pdf" size="658815" user="MichaelTraxler" version="1.1"
Added:
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META FILEATTACHMENT attr="" comment="AddOn Board with 8 NIM and 16 differential connectors" date="1371714987" name="GPIN_AddOn1_alles.pdf" path="GPIN_AddOn1_alles.pdf" size="458828" user="CahitUgur" version="1.1"
Revision 23
07 May 2013 - Main.MichaelTraxler
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

TRBv3

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Added:
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PADIWA (PANDA-DIRC-WASA)

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META FILEATTACHMENT attr="" comment="CBM-TOF FEE schematics" date="1365151304" name="CBM-TOF-FEE1-SCM-NEU.pdf" path="CBM-TOF-FEE1-SCM-NEU.pdf" size="96185" user="CahitUgur" version="1.1"
META FILEATTACHMENT attr="" comment="Padiwa2 Schematics, with MMCX connectors" date="1366804044" name="PADIWA2-all.pdf" path="PADIWA2-all.pdf" size="760619" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="Padiwa3, connector suited for PANDA-MCP (2mm pitch, %_Q_%alternating signals%_Q_% pinout)" date="1366804078" name="PADIWA3-all.pdf" path="PADIWA3-all.pdf" size="1127365" user="MichaelTraxler" version="1.1"
Added:
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META FILEATTACHMENT attr="" comment="TRB3 CTS AddOn1" date="1367942902" name="trb3cts_addon1_alles.pdf" path="trb3cts_addon1_alles.pdf" size="658815" user="MichaelTraxler" version="1.1"
Revision 22
24 Apr 2013 - Main.MichaelTraxler
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

TRBv3

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PADIWA (PANDA-DIRC-WASA)

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  • PADIWA2-all.pdf: Padiwa2 Schematics, with MMCX connectors
  • PADIWA3-all.pdf: Padiwa3, connector suited for PANDA-MCP (2mm pitch, "alternating signals" pinout)
 

Line: 79 to 71
 
META FILEATTACHMENT attr="" comment="Padiwa2 Schematics, with MMCX connectors" date="1354897420" name="PADIWA2-alles.pdf" path="PADIWA2-alles.pdf" size="670876" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="Padiwa3 schematics and Layout, for PANDA-MCPs" date="1363000885" name="PADIWA3-alles.pdf" path="PADIWA3-alles.pdf" size="1044734" user="MichaelTraxler" version="1.2"
META FILEATTACHMENT attr="" comment="CBM-TOF FEE schematics" date="1365151304" name="CBM-TOF-FEE1-SCM-NEU.pdf" path="CBM-TOF-FEE1-SCM-NEU.pdf" size="96185" user="CahitUgur" version="1.1"
Added:
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META FILEATTACHMENT attr="" comment="Padiwa2 Schematics, with MMCX connectors" date="1366804044" name="PADIWA2-all.pdf" path="PADIWA2-all.pdf" size="760619" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="Padiwa3, connector suited for PANDA-MCP (2mm pitch, %_Q_%alternating signals%_Q_% pinout)" date="1366804078" name="PADIWA3-all.pdf" path="PADIWA3-all.pdf" size="1127365" user="MichaelTraxler" version="1.1"
Revision 21
05 Apr 2013 - Main.CahitUgur
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

TRBv3

Line: 34 to 34
 

CBM-RICH

Added:
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>

CBM-TOF

 

Bugs

The list of bugs and limitations is available in the TRB3 Handbook and Documentation
Line: 74 to 78
 
META FILEATTACHMENT attr="" comment="Padiwa1 schematics" date="1354897268" name="WASA1-alles.pdf" path="WASA1-alles.pdf" size="804740" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="Padiwa2 Schematics, with MMCX connectors" date="1354897420" name="PADIWA2-alles.pdf" path="PADIWA2-alles.pdf" size="670876" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="Padiwa3 schematics and Layout, for PANDA-MCPs" date="1363000885" name="PADIWA3-alles.pdf" path="PADIWA3-alles.pdf" size="1044734" user="MichaelTraxler" version="1.2"
Added:
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META FILEATTACHMENT attr="" comment="CBM-TOF FEE schematics" date="1365151304" name="CBM-TOF-FEE1-SCM-NEU.pdf" path="CBM-TOF-FEE1-SCM-NEU.pdf" size="96185" user="CahitUgur" version="1.1"
Revision 20
11 Mar 2013 - Main.MichaelTraxler
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

TRBv3

Line: 73 to 73
 
META FILEATTACHMENT attr="" comment="CBM-RICH-FEE" date="1335175515" moveby="MichaelTraxler" movedto="DaqSlowControl.TDCReadoutBoardV3" movedwhen="1347378445" movefrom="DaqSlowControl.TDCReadoutBoardV2" name="cmb_rich_fee1-alles.pdf" path="cmb_rich_fee1-alles.pdf" size="1273907" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="Padiwa1 schematics" date="1354897268" name="WASA1-alles.pdf" path="WASA1-alles.pdf" size="804740" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="Padiwa2 Schematics, with MMCX connectors" date="1354897420" name="PADIWA2-alles.pdf" path="PADIWA2-alles.pdf" size="670876" user="MichaelTraxler" version="1.1"
Changed:
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META FILEATTACHMENT attr="" comment="padiwa3, connector suited for PANDA-MCP (2mm pitch, %_Q_%alternating signals%_Q_% pinout)" date="1354897570" name="PADIWA3-alles.pdf" path="PADIWA3-alles.pdf" size="459699" user="MichaelTraxler" version="1.1"
>
>
META FILEATTACHMENT attr="" comment="Padiwa3 schematics and Layout, for PANDA-MCPs" date="1363000885" name="PADIWA3-alles.pdf" path="PADIWA3-alles.pdf" size="1044734" user="MichaelTraxler" version="1.2"
Revision 19
04 Jan 2013 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

TRBv3

Line: 69 to 69
 
META FILEATTACHMENT attr="" comment="TRB3-AddOn to convert from the new 208-pin connector to the 80-pin Kel connectors" date="1316694575" name="ADDON1ADA1_alles.pdf" path="ADDON1ADA1_alles.pdf" size="256910" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="MultiTestAddOn" date="1335201611" name="MultiTestAddon1_alles.pdf" path="MultiTestAddon1_alles.pdf" size="945837" user="JanMichel" version="1.1"
META FILEATTACHMENT attr="" comment="SFP AddOn" date="1335201625" name="SFP-Addon1_alles.pdf" path="SFP-Addon1_alles.pdf" size="446334" user="JanMichel" version="1.1"
Deleted:
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<
META FILEATTACHMENT attr="" comment="Panda DIRC / Wasa front-end board" date="1346666272" name="panda-dirc-wasa1.pdf" path="panda-dirc-wasa1.pdf" size="247609" user="JanMichel" version="1.1"
 
META FILEATTACHMENT attr="" comment="AddOn_4CONN2, 4 connectors for each 16 channels + SPI" date="1347228721" moveby="MichaelTraxler" movedto="DaqSlowControl.TDCReadoutBoardV3" movedwhen="1347376124" movefrom="DaqSlowControl.TDCReadoutBoardV2" name="ADDON_4CONN2-alles.pdf" path="ADDON_4CONN2-alles.pdf" size="282073" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="CBM-RICH-FEE" date="1335175515" moveby="MichaelTraxler" movedto="DaqSlowControl.TDCReadoutBoardV3" movedwhen="1347378445" movefrom="DaqSlowControl.TDCReadoutBoardV2" name="cmb_rich_fee1-alles.pdf" path="cmb_rich_fee1-alles.pdf" size="1273907" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="Padiwa1 schematics" date="1354897268" name="WASA1-alles.pdf" path="WASA1-alles.pdf" size="804740" user="MichaelTraxler" version="1.1"
Revision 18
07 Dec 2012 - Main.MichaelTraxler
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

TRBv3

Line: 24 to 24
 

PADIWA (PANDA-DIRC-WASA)

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Line: 66 to 72
 
META FILEATTACHMENT attr="" comment="Panda DIRC / Wasa front-end board" date="1346666272" name="panda-dirc-wasa1.pdf" path="panda-dirc-wasa1.pdf" size="247609" user="JanMichel" version="1.1"
META FILEATTACHMENT attr="" comment="AddOn_4CONN2, 4 connectors for each 16 channels + SPI" date="1347228721" moveby="MichaelTraxler" movedto="DaqSlowControl.TDCReadoutBoardV3" movedwhen="1347376124" movefrom="DaqSlowControl.TDCReadoutBoardV2" name="ADDON_4CONN2-alles.pdf" path="ADDON_4CONN2-alles.pdf" size="282073" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="CBM-RICH-FEE" date="1335175515" moveby="MichaelTraxler" movedto="DaqSlowControl.TDCReadoutBoardV3" movedwhen="1347378445" movefrom="DaqSlowControl.TDCReadoutBoardV2" name="cmb_rich_fee1-alles.pdf" path="cmb_rich_fee1-alles.pdf" size="1273907" user="MichaelTraxler" version="1.1"
Added:
>
>
META FILEATTACHMENT attr="" comment="Padiwa1 schematics" date="1354897268" name="WASA1-alles.pdf" path="WASA1-alles.pdf" size="804740" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="Padiwa2 Schematics, with MMCX connectors" date="1354897420" name="PADIWA2-alles.pdf" path="PADIWA2-alles.pdf" size="670876" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="padiwa3, connector suited for PANDA-MCP (2mm pitch, %_Q_%alternating signals%_Q_% pinout)" date="1354897570" name="PADIWA3-alles.pdf" path="PADIWA3-alles.pdf" size="459699" user="MichaelTraxler" version="1.1"
Revision 17
11 Sep 2012 - Main.MichaelTraxler
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

TRBv3

Line: 22 to 22
 
Added:
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PADIWA (PANDA-DIRC-WASA)

 
Added:
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CBM-RICH

 

Bugs

The list of bugs and limitations is available in the TRB3 Handbook and Documentation
Line: 56 to 64
 
META FILEATTACHMENT attr="" comment="MultiTestAddOn" date="1335201611" name="MultiTestAddon1_alles.pdf" path="MultiTestAddon1_alles.pdf" size="945837" user="JanMichel" version="1.1"
META FILEATTACHMENT attr="" comment="SFP AddOn" date="1335201625" name="SFP-Addon1_alles.pdf" path="SFP-Addon1_alles.pdf" size="446334" user="JanMichel" version="1.1"
META FILEATTACHMENT attr="" comment="Panda DIRC / Wasa front-end board" date="1346666272" name="panda-dirc-wasa1.pdf" path="panda-dirc-wasa1.pdf" size="247609" user="JanMichel" version="1.1"
Added:
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META FILEATTACHMENT attr="" comment="AddOn_4CONN2, 4 connectors for each 16 channels + SPI" date="1347228721" moveby="MichaelTraxler" movedto="DaqSlowControl.TDCReadoutBoardV3" movedwhen="1347376124" movefrom="DaqSlowControl.TDCReadoutBoardV2" name="ADDON_4CONN2-alles.pdf" path="ADDON_4CONN2-alles.pdf" size="282073" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="CBM-RICH-FEE" date="1335175515" moveby="MichaelTraxler" movedto="DaqSlowControl.TDCReadoutBoardV3" movedwhen="1347378445" movefrom="DaqSlowControl.TDCReadoutBoardV2" name="cmb_rich_fee1-alles.pdf" path="cmb_rich_fee1-alles.pdf" size="1273907" user="MichaelTraxler" version="1.1"
Revision 16
03 Sep 2012 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

TRBv3

Line: 18 to 18
 
  • plot.tgz: Plot of Top and Bottom side of the PCB as a b&w plot
  • doc.tgz: All PCB documentation
Changed:
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AddOn Schematics

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AddOn Schematics

 
Changed:
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Bugs

The list of bugs and limitations is available in the TRB3 Handbook and Documentation
Line: 53 to 55
 
META FILEATTACHMENT attr="" comment="TRB3-AddOn to convert from the new 208-pin connector to the 80-pin Kel connectors" date="1316694575" name="ADDON1ADA1_alles.pdf" path="ADDON1ADA1_alles.pdf" size="256910" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="MultiTestAddOn" date="1335201611" name="MultiTestAddon1_alles.pdf" path="MultiTestAddon1_alles.pdf" size="945837" user="JanMichel" version="1.1"
META FILEATTACHMENT attr="" comment="SFP AddOn" date="1335201625" name="SFP-Addon1_alles.pdf" path="SFP-Addon1_alles.pdf" size="446334" user="JanMichel" version="1.1"
Added:
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META FILEATTACHMENT attr="" comment="Panda DIRC / Wasa front-end board" date="1346666272" name="panda-dirc-wasa1.pdf" path="panda-dirc-wasa1.pdf" size="247609" user="JanMichel" version="1.1"
Revision 15
07 May 2012 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

TRBv3

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After collecting all the information from the future users of the TRBv3 we came to the following specification:
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Layout and Feature Proposals

 

Finished board

Line: 10 to 12
 

Schematics and Layout

Deleted:
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The layout of the TRBv3 has been finished yesterday (!?) and ordered today (7.07.). The delivery time is 5 weeks!

Here are the schematics:
 
Changed:
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and the wirelist and the .lpf files for the FPGAs (have to be adjusted to be able to use one file for all 4 FPGAs -> Jan):

and the clocking and trigger distribution scheme as well as default configuration for Clock Managers:
>
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  • TRBv3_FPGAs.tar.gz: and the wirelist and the .lpf files for the FPGAs (have to be adjusted to be able to use one file for all 4 FPGAs -> Jan):
 
Changed:
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and the top and bottom view of the PCB as a b&w plot:
  • plot.tgz: Plot of Top and Bottom side of the PCB

more information about the PCB:
>
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  • plot.tgz: Plot of Top and Bottom side of the PCB as a b&w plot
 
Added:
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AddOn Schematics

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Bugs

Changed:
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  • The SFPs are missing LEDs - so no information about link status
  • The outputs of the CLK5410 chips are not independent: Two outputs share some settings - regarding this the connection is far from optimal, e.g. the clock to the serdes from FPGA1 is not independent from clock to GPLL input on FPGA4 etc.
  • SFP cages could have been distributed differently. Now, all TrbNet links (SFP1-4) are on one side and all GbE capable links on the other two (SFP5-8). Usually only few ports are in use, so a mix would be better.
  • TRB_TO_ADDON_CLOCK is located on a port that does not support LVDS output
  • All pins connected to a DLL and PLL are Input only and can not be used as outputs! On the central FPGA, these are pins FS_PE 4,5,7,8 and ADO_TTL 23,26,30,46
  • SPARE_LINE between FPGA and AddOn-Connector are connected to Feedback input of PLL, not the normal input to PLL
  • On peripheral FPGA lines 8 and 9 of DQUR0 are input only - they are removed from the LPF for now.
  • Both GPLL inputs to peripheral FPGA are not usable - they are connected to Feedback input instead of normal input of PLL. They can still be used through normal routing, but source synchronous operation is not possible.
  • The JTAG Connector is wrong. The line labeled TDI is TDO and vice versa. Be careful, this is a JTAG-cable-killer!
  • The 48V-to-6V converter gets quite hot without air-flow. When AddOns are mounted, the fan must be installed on the short side of the TRB, not on the long one.

Layout Proposal (obsolete):

Key Features

  • 4 times LFE3-70E(A)-8FN672C for TDC (+ future applications, as e.g. ADC-readout )
  • 1 central LFE3-150EA-8FN1156C

all at highest speed grade to reduce the development time. ECP3 70/95/150 are supposed to be mostly pin-compatible, so FPGA can be exchanged later if necessary. (Confirmation of Lattice arrived.)

  • smaller 48V power supply, based on Vicors BCM: http://cdn.vicorpower.com/documents/datasheets/BCM_48VFamily_DS.pdf, B048F060T24 is the type
  • all other PoL regulators based on the Enpirion Products (evaluation board and devices are here at GSI): http://www.enpirion.com/products-en5396qi.htm or similar
  • Add pads / holes around DCDC converters to replace them with an addon board (to use linear regulators in case the DCDC converters produce too much noise in analog data)
  • 2 times 2 SFPs to the central FPGA: 2 for Ethernet and 2 for TRBNet (for example). The position is not really fixed as shown in the layout-proposal. Can be spread over the board.

clock

For the TDC functionality a direct clock with fanout will give a better performance. Here TI is very good, as we know: http://focus.ti.com/docs/prod/folders/print/cdclvd1216.html The TDC needs a 200MHz clock (SiS.type as on all other boards). -> 100 MHz system clock can easily be generated from this clock. Thus use two onboard clock networks: 125 MHz and 200 MHz. Proposed layout: 2 CLK5410 chips, both inputs on both chips equipped with oscillators (one input used, one free). From one CLK5410 chip put one line to one Serdes of each FPGA and one line to a PCLK input (2,3,6,7). From the other CLK5410 chip put one line to one Serdes of each FPGA and one line to a GPLL input on the left/right side of each FPGA. But we need the direct clock (200MHz after fanout) to a clock input of each FPGA for the TDC. New requirement (R3B): The board has to be able to run on an external clock. So, one differential line from the RJ45 connector schoul go to one of the clock managers. This will do what we need.

Connectors

  • we leave the add-on connectors as they are on v2 controlled by the central FPGA.

  • The connectors to each FPGA should be Samtec: QMS-104-09.75-L-D-A (mating part: QFS-104-06.25-L-D-A): Length 8,5cm These high speed connectors are similar to the AddOn connectors of the TRBv2, but are more rugged. They provide 208 pins + 3 power blades. Used by Jan Hoffmann and recommended by him.

The idea is to use the lower 80 pins exactly as used on the TRBv2 to be able to use the TRBv2 in the existing setups. (A small adapter board to the KEL-connectors has to be built for that). On the other hand, these connectors allow to build small AddOns which have the additional possibility to connect to 128 more pins (+ power). This allows to read out with the FPGA (LFE3-70) on the TRB for example ADCs or other devices. Then we have the TDC and ADC data all available in one FPGA and in total a board with 128 channels. Application: ECal for example.

The pinout of the remaining 128 pins has to be chosen carefully (to be done). Please help! http://www.samtec.com/documents/webfiles/pdf/qms.pdf

  • Standard reference time input: This then is fed to a fan-out chip, which will be fed to the FPGAs (twice as Marek said). And a RJ45 as secondary reference time input. (The input of the fanout-chips can select between two inputs. This can be done via a jumper.)

  • Additional auxilary connectors, like RJ45 + a normal pitch pin-header, all connected to the central FPGA. *Many LEDs! (Please label them LED1..8, not dgood, dwait etc.) maybe 4 for each FPGA. And a test connector for each of the 4 FPGAs.

Connection between FPGA:

  • SERDES connections
  • Each of the TDC-FPGAs has two SERDES connections to the central FPGA, coming from two QUADS. If possible, put one line of one quad to the mini-addon-connector. Put a set of 12 LVCMOS25 lines between the central FPGA and each of the other FPGAs
All 4 FPGAs have identical schematics and layout!

  • Each FPGA gets a FLASH to boot from.
From the MDC-Hub2 we learned: Connect the programming lines from all flashs to the central FPGA - this way a broken Flash can be restored since the central FPGA is not affected by an upgrade of the other four FPGA. (There is no nice way to recover the central FPGA, but this one will be upgraded much more seldomly). (see comments)

  • JTAG chain.

  • DDR2-3 RAM and SRAM I would skip on the 4 FPGAs, I don't see the obvious application.
  • Maybe an SRAM on the central FPGA. DDR3 is tricky and not !

After reading TN1180 I would rather avoid DDR unless we really need it. If we need it we have to write vhdl code with proper constraints and without any drc errors before pin assignment. (Which is the usual way how to design boards in general...)
>
>
The list of bugs and limitations is available in the TRB3 Handbook and Documentation
 
Changed:
<
<
  • Two bit coding input to select the FPGA number - like on the MDC Hub2
>
>

Available Boards

 
Added:
>
>

Further Documentation

 
Deleted:
<
<

Manpower

 
Deleted:
<
<
  • Marcin: schematics: started on 2011-02-07
  • Pinout definition: all, please help
  • Greg can start with the UDP-communication protocol, replacing the ETRAX by a PC: start 2011-02-14
  • Layout and production: Peter and Michael
  • TRBNet implementation: Jan
  • TDC-implementation: Cahit + Eugen
  • TDC-Data-analyis, feature check etc.: Marek
 

-- MichaelTraxler - 11 Feb 2011
Revision 14
23 Apr 2012 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

TRBv3

Line: 10 to 10
 

Schematics and Layout

Changed:
<
<
The layout of the TRBv3 has been finished yesterday and ordered today (7.07.). The delivery time is 5 weeks!
>
>
The layout of the TRBv3 has been finished yesterday (!?) and ordered today (7.07.). The delivery time is 5 weeks!
 

Here are the schematics:
Line: 27 to 27
 

more information about the PCB:
Changed:
<
<

the first AddOn, just a cable adaptor.
>
>

AddOn Schematics

 
  • ADDON1ADA1_alles.pdf: TRB3-AddOn to convert from the new 208-pin connector to the 80-pin Kel connectors
Added:
>
>
 

Bugs

  • The SFPs are missing LEDs - so no information about link status
Line: 138 to 140
 
META FILEATTACHMENT attr="" comment="All PCB documentation" date="1310051411" name="doc.tgz" path="doc.tgz" size="6938977" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="Clock and trigger distribution on TRB3" date="1314177987" name="trb3_clock_distribution..png" path="trb3_clock_distribution..png" size="102152" user="JanMichel" version="1.1"
META FILEATTACHMENT attr="" comment="TRB3-AddOn to convert from the new 208-pin connector to the 80-pin Kel connectors" date="1316694575" name="ADDON1ADA1_alles.pdf" path="ADDON1ADA1_alles.pdf" size="256910" user="MichaelTraxler" version="1.1"
Added:
>
>
META FILEATTACHMENT attr="" comment="MultiTestAddOn" date="1335201611" name="MultiTestAddon1_alles.pdf" path="MultiTestAddon1_alles.pdf" size="945837" user="JanMichel" version="1.1"
META FILEATTACHMENT attr="" comment="SFP AddOn" date="1335201625" name="SFP-Addon1_alles.pdf" path="SFP-Addon1_alles.pdf" size="446334" user="JanMichel" version="1.1"
Revision 13
28 Sep 2011 - Main.MichaelTraxler
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

TRBv3

After collecting all the information from the future users of the TRBv3 we came to the following specification:
Added:
>
>

Finished board

TRB3 picture
 

Schematics and Layout

The layout of the TRBv3 has been finished yesterday and ordered today (7.07.). The delivery time is 5 weeks!
Revision 12
22 Sep 2011 - Main.MichaelTraxler
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

TRBv3

Line: 24 to 24
  more information about the PCB:
Added:
>
>
the first AddOn, just a cable adaptor.
  • ADDON1ADA1_alles.pdf: TRB3-AddOn to convert from the new 208-pin connector to the 80-pin Kel connectors
 

Bugs

  • The SFPs are missing LEDs - so no information about link status
Line: 122 to 124
 

Changed:
<
<
  • ADDON1ADA1_alles.pdf: TRB3-AddOn to convert from the new 208-pin connector to the 80-pin Kel connectors
>
>
 

META FILEATTACHMENT attr="" comment="Layout proposal" date="1297418191" name="TRB3_layout_proposal1.pdf" path="TRB3_layout_proposal1.pdf" size="22263" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="TRB3 updated layout" date="1302528124" name="TRBv3plain.png" path="TRBv3 plain.png" size="64168" user="JanMichel" version="1.1"
Revision 11
22 Sep 2011 - Main.MichaelTraxler
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

TRBv3

Line: 122 to 122
 

Added:
>
>
  • ADDON1ADA1_alles.pdf: TRB3-AddOn to convert from the new 208-pin connector to the 80-pin Kel connectors
 
META FILEATTACHMENT attr="" comment="Layout proposal" date="1297418191" name="TRB3_layout_proposal1.pdf" path="TRB3_layout_proposal1.pdf" size="22263" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="TRB3 updated layout" date="1302528124" name="TRBv3plain.png" path="TRBv3 plain.png" size="64168" user="JanMichel" version="1.1"
META FILEATTACHMENT attr="" comment="FPGA lpf files" date="1310043445" name="TRBv3_FPGAs.tar.gz" path="TRBv3_FPGAs.tar.gz" size="66421" user="MichaelTraxler" version="1.1"
Line: 129 to 131
 
META FILEATTACHMENT attr="" comment="Plot of Top and Bottom side of the PCB" date="1310047115" name="plot.tgz" path="plot.tgz" size="1385464" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="All PCB documentation" date="1310051411" name="doc.tgz" path="doc.tgz" size="6938977" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="Clock and trigger distribution on TRB3" date="1314177987" name="trb3_clock_distribution..png" path="trb3_clock_distribution..png" size="102152" user="JanMichel" version="1.1"
Added:
>
>
META FILEATTACHMENT attr="" comment="TRB3-AddOn to convert from the new 208-pin connector to the 80-pin Kel connectors" date="1316694575" name="ADDON1ADA1_alles.pdf" path="ADDON1ADA1_alles.pdf" size="256910" user="MichaelTraxler" version="1.1"
Revision 10
01 Sep 2011 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

TRBv3

Line: 34 to 34
 
  • SPARE_LINE between FPGA and AddOn-Connector are connected to Feedback input of PLL, not the normal input to PLL
  • On peripheral FPGA lines 8 and 9 of DQUR0 are input only - they are removed from the LPF for now.
  • Both GPLL inputs to peripheral FPGA are not usable - they are connected to Feedback input instead of normal input of PLL. They can still be used through normal routing, but source synchronous operation is not possible.
Added:
>
>
  • The JTAG Connector is wrong. The line labeled TDI is TDO and vice versa. Be careful, this is a JTAG-cable-killer!
  • The 48V-to-6V converter gets quite hot without air-flow. When AddOns are mounted, the fan must be installed on the short side of the TRB, not on the long one.
 

Layout Proposal (obsolete):

Revision 9
25 Aug 2011 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

TRBv3

Line: 31 to 31
 
  • SFP cages could have been distributed differently. Now, all TrbNet links (SFP1-4) are on one side and all GbE capable links on the other two (SFP5-8). Usually only few ports are in use, so a mix would be better.
  • TRB_TO_ADDON_CLOCK is located on a port that does not support LVDS output
  • All pins connected to a DLL and PLL are Input only and can not be used as outputs! On the central FPGA, these are pins FS_PE 4,5,7,8 and ADO_TTL 23,26,30,46
Changed:
<
<
>
>
  • SPARE_LINE between FPGA and AddOn-Connector are connected to Feedback input of PLL, not the normal input to PLL
  • On peripheral FPGA lines 8 and 9 of DQUR0 are input only - they are removed from the LPF for now.
  • Both GPLL inputs to peripheral FPGA are not usable - they are connected to Feedback input instead of normal input of PLL. They can still be used through normal routing, but source synchronous operation is not possible.
 

Layout Proposal (obsolete):

Revision 8
24 Aug 2011 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

TRBv3

Line: 29 to 29
 
  • The SFPs are missing LEDs - so no information about link status
  • The outputs of the CLK5410 chips are not independent: Two outputs share some settings - regarding this the connection is far from optimal, e.g. the clock to the serdes from FPGA1 is not independent from clock to GPLL input on FPGA4 etc.
  • SFP cages could have been distributed differently. Now, all TrbNet links (SFP1-4) are on one side and all GbE capable links on the other two (SFP5-8). Usually only few ports are in use, so a mix would be better.
Added:
>
>
  • TRB_TO_ADDON_CLOCK is located on a port that does not support LVDS output
  • All pins connected to a DLL and PLL are Input only and can not be used as outputs! On the central FPGA, these are pins FS_PE 4,5,7,8 and ADO_TTL 23,26,30,46
 

Layout Proposal (obsolete):

Revision 7
24 Aug 2011 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

TRBv3

Line: 14 to 14
  and the wirelist and the .lpf files for the FPGAs (have to be adjusted to be able to use one file for all 4 FPGAs -> Jan):
Added:
>
>
and the clocking and trigger distribution scheme as well as default configuration for Clock Managers:
  and the top and bottom view of the PCB as a b&w plot:
  • plot.tgz: Plot of Top and Bottom side of the PCB
Line: 22 to 25
 
Added:
>
>

Bugs

  • The SFPs are missing LEDs - so no information about link status
  • The outputs of the CLK5410 chips are not independent: Two outputs share some settings - regarding this the connection is far from optimal, e.g. the clock to the serdes from FPGA1 is not independent from clock to GPLL input on FPGA4 etc.
  • SFP cages could have been distributed differently. Now, all TrbNet links (SFP1-4) are on one side and all GbE capable links on the other two (SFP5-8). Usually only few ports are in use, so a mix would be better.
 

Layout Proposal (obsolete):

Line: 111 to 122
 
META FILEATTACHMENT attr="" comment="final schematics" date="1310043554" name="trbv3_SCHEMATIC_michael.pdf" path="trbv3_SCHEMATIC_michael.pdf" size="1039109" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="Plot of Top and Bottom side of the PCB" date="1310047115" name="plot.tgz" path="plot.tgz" size="1385464" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="All PCB documentation" date="1310051411" name="doc.tgz" path="doc.tgz" size="6938977" user="MichaelTraxler" version="1.1"
Added:
>
>
META FILEATTACHMENT attr="" comment="Clock and trigger distribution on TRB3" date="1314177987" name="trb3_clock_distribution..png" path="trb3_clock_distribution..png" size="102152" user="JanMichel" version="1.1"
Revision 6
07 Jul 2011 - Main.MichaelTraxler
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

TRBv3

Line: 6 to 6
 

Schematics and Layout

Changed:
<
<
The layout of the TRBv3 has been finished yesterday and ordered today (7.07.). The delivery time is 6 weeks!
>
>
The layout of the TRBv3 has been finished yesterday and ordered today (7.07.). The delivery time is 5 weeks!
 

Here are the schematics:
Line: 19 to 18
 
  • plot.tgz: Plot of Top and Bottom side of the PCB
Added:
>
>
more information about the PCB:
 

Layout Proposal (obsolete):

Line: 107 to 110
 
META FILEATTACHMENT attr="" comment="FPGA lpf files" date="1310043445" name="TRBv3_FPGAs.tar.gz" path="TRBv3_FPGAs.tar.gz" size="66421" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="final schematics" date="1310043554" name="trbv3_SCHEMATIC_michael.pdf" path="trbv3_SCHEMATIC_michael.pdf" size="1039109" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="Plot of Top and Bottom side of the PCB" date="1310047115" name="plot.tgz" path="plot.tgz" size="1385464" user="MichaelTraxler" version="1.1"
Added:
>
>
META FILEATTACHMENT attr="" comment="All PCB documentation" date="1310051411" name="doc.tgz" path="doc.tgz" size="6938977" user="MichaelTraxler" version="1.1"
Revision 5
07 Jul 2011 - Main.MichaelTraxler
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

TRBv3

After collecting all the information from the future users of the TRBv3 we came to the following specification:
Added:
>
>

Schematics and Layout

 
Changed:
<
<

Layout Proposal:

>
>
The layout of the TRBv3 has been finished yesterday and ordered today (7.07.). The delivery time is 6 weeks!

Here are the schematics:

and the wirelist and the .lpf files for the FPGAs (have to be adjusted to be able to use one file for all 4 FPGAs -> Jan):

and the top and bottom view of the PCB as a b&w plot:

  • plot.tgz: Plot of Top and Bottom side of the PCB

Layout Proposal (obsolete):

 

Line: 86 to 100
 

-- MichaelTraxler - 11 Feb 2011
Added:
>
>
 
META FILEATTACHMENT attr="" comment="Layout proposal" date="1297418191" name="TRB3_layout_proposal1.pdf" path="TRB3_layout_proposal1.pdf" size="22263" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="TRB3 updated layout" date="1302528124" name="TRBv3plain.png" path="TRBv3 plain.png" size="64168" user="JanMichel" version="1.1"
Added:
>
>
META FILEATTACHMENT attr="" comment="FPGA lpf files" date="1310043445" name="TRBv3_FPGAs.tar.gz" path="TRBv3_FPGAs.tar.gz" size="66421" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="final schematics" date="1310043554" name="trbv3_SCHEMATIC_michael.pdf" path="trbv3_SCHEMATIC_michael.pdf" size="1039109" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="Plot of Top and Bottom side of the PCB" date="1310047115" name="plot.tgz" path="plot.tgz" size="1385464" user="MichaelTraxler" version="1.1"
Revision 4
11 Apr 2011 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

TRBv3

Line: 8 to 8
 

Layout Proposal:

Changed:
<
<
>
>
  • TRB3 updated layout:
    TRB3 updated layout
 

Key Features

Line: 85 to 86
 

-- MichaelTraxler - 11 Feb 2011
Deleted:
<
<
 
META FILEATTACHMENT attr="" comment="Layout proposal" date="1297418191" name="TRB3_layout_proposal1.pdf" path="TRB3_layout_proposal1.pdf" size="22263" user="MichaelTraxler" version="1.1"
Added:
>
>
META FILEATTACHMENT attr="" comment="TRB3 updated layout" date="1302528124" name="TRBv3plain.png" path="TRBv3 plain.png" size="64168" user="JanMichel" version="1.1"
Revision 3
11 Feb 2011 - Main.MichaelTraxler
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

TRBv3

Line: 59 to 59
 
  • Each of the TDC-FPGAs has two SERDES connections to the central FPGA, coming from two QUADS. If possible, put one line of one quad to the mini-addon-connector. Put a set of 12 LVCMOS25 lines between the central FPGA and each of the other FPGAs
All 4 FPGAs have identical schematics and layout!
Changed:
<
<

- Each FPGA gets a FLASH to boot from.
>
>
  • Each FPGA gets a FLASH to boot from.
  From the MDC-Hub2 we learned: Connect the programming lines from all flashs to the central FPGA - this way a broken Flash can be restored since the central FPGA is not affected by an upgrade of the other four FPGA. (There is no nice way to recover the central FPGA, but this one will be upgraded much more seldomly). (see comments)
Deleted:
<
<
- JTAG chain.
 
Changed:
<
<
- DDR2-3 RAM and SRAM I would skip on the 4 FPGAs, I don't see the obvious application. - Maybe an SRAM on the central FPGA. DDR3 is tricky and not !
>
>
  • JTAG chain.

  • DDR2-3 RAM and SRAM I would skip on the 4 FPGAs, I don't see the obvious application.
  • Maybe an SRAM on the central FPGA. DDR3 is tricky and not !
  After reading TN1180 I would rather avoid DDR unless we really need it. If we need it we have to write vhdl code with proper constraints and without any drc errors before pin assignment. (Which is the usual way how to design boards in general...)
Changed:
<
<
- Two bit coding input to select the FPGA number - like on the MDC Hub2
>
>
  • Two bit coding input to select the FPGA number - like on the MDC Hub2
 
Deleted:
<
<
What else did I miss?
 
Changed:
<
<
So, Marcin can start with the schematics. And Greg can start with the UDP-communication protocol, replacing the ETRAX by a PC/Plug-Computer.
>
>

Manpower

 
Added:
>
>
  • Marcin: schematics: started on 2011-02-07
  • Pinout definition: all, please help
  • Greg can start with the UDP-communication protocol, replacing the ETRAX by a PC: start 2011-02-14
  • Layout and production: Peter and Michael
  • TRBNet implementation: Jan
  • TDC-implementation: Cahit + Eugen
  • TDC-Data-analyis, feature check etc.: Marek
 

-- MichaelTraxler - 11 Feb 2011
Revision 2
11 Feb 2011 - Main.MichaelTraxler
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

TRBv3

Line: 16 to 16
 
  • 1 central LFE3-150EA-8FN1156C

all at highest speed grade to reduce the development time.
Changed:
<
<
ECP3 70/95/150 are supposed to be mostly pin-compatible, so FPGA can be exchanged later if necessary Request to Lattice is sent and wating for reply (10.02.2011)
>
>
ECP3 70/95/150 are supposed to be mostly pin-compatible, so FPGA can be exchanged later if necessary. (Confirmation of Lattice arrived.)
 
Changed:
<
<
- smaller 48V power supply, based on Vicors BCM: http://cdn.vicorpower.com/documents/datasheets/BCM_48VFamily_DS.pdf - B048F060T24 is the type - all other PoL regulators based on the Enpirion Products (evaluation board and devices are here at GSI): http://www.enpirion.com/products-en5396qi.htm or similar - Add pads / holes around DCDC converters to replace them with an addon board (to use linear regulators in case the DCDC converters produce too much noise in analog data)
>
>
  • smaller 48V power supply, based on Vicors BCM: http://cdn.vicorpower.com/documents/datasheets/BCM_48VFamily_DS.pdf, B048F060T24 is the type
  • all other PoL regulators based on the Enpirion Products (evaluation board and devices are here at GSI): http://www.enpirion.com/products-en5396qi.htm or similar
  • Add pads / holes around DCDC converters to replace them with an addon board (to use linear regulators in case the DCDC converters produce too much noise in analog data)
  • 2 times 2 SFPs to the central FPGA: 2 for Ethernet and 2 for TRBNet (for example). The position is not really fixed as shown in the layout-proposal. Can be spread over the board.
 
Added:
>
>

clock

 
Deleted:
<
<
- 2 times 2 SFPs to the central FPGA: 2 for Ethernet and 2 for TRBNet (for example). The position is not really fixed as shown in the layout-proposal. Can be spread over the board.

- clock: Lattice Clock Manager is working for the FPGAs and SERDESes http://www.latticesemi.com/products/ispclock/index.cfm?source=topnav (CLK5406 is used on the PEXOR3)
  For the TDC functionality a direct clock with fanout will give a better performance.
Changed:
<
<
Here TI is very good, as we know: http://focus.ti.com/docs/prod/folders/print/cdclvd1216.html
>
>
Here TI is very good, as we know: http://focus.ti.com/docs/prod/folders/print/cdclvd1216.html
  The TDC needs a 200MHz clock (SiS.type as on all other boards). -> 100 MHz system clock can easily be generated from this clock. Thus use two onboard clock networks: 125 MHz and 200 MHz. Proposed layout: 2 CLK5410 chips, both inputs on both chips equipped with oscillators (one input used, one free). From one CLK5410 chip put one line to one Serdes of each FPGA and one line to a PCLK input (2,3,6,7). From the other CLK5410 chip put one line to one Serdes of each FPGA and one line to a GPLL input on the left/right side of each FPGA. But we need the direct clock (200MHz after fanout) to a clock input of each FPGA for the TDC. New requirement (R3B): The board has to be able to run on an external clock. So, one differential line from the RJ45 connector schoul go to one of the clock managers. This will do what we need.
Changed:
<
<
Connectors: - this is obvious: we leave add-on connectors as they are on v2 controlled by the central FPGA. - The connectors to each FPGA can be Samtec: QMS-104-09.75-L-D-A (mating part: QFS-104-06.25-L-D-A): Length 8,5cm These high speed connectors are similar to the AddOn connectors of the TRBv2, but are more rugged. They provide 208 pins + 3 power blades. Used by Jan Hoffmann and recommended by him.
>
>

Connectors

  • we leave the add-on connectors as they are on v2 controlled by the central FPGA.

  • The connectors to each FPGA should be Samtec: QMS-104-09.75-L-D-A (mating part: QFS-104-06.25-L-D-A): Length 8,5cm These high speed connectors are similar to the AddOn connectors of the TRBv2, but are more rugged. They provide 208 pins + 3 power blades. Used by Jan Hoffmann and recommended by him.
 

The idea is to use the lower 80 pins exactly as used on the TRBv2 to be able to use the TRBv2 in the existing setups. (A small adapter board to the KEL-connectors has to be built for that). On the other hand, these connectors allow to build small AddOns which have the additional possibility to connect to 128 more pins (+ power). This allows to read out with the FPGA (LFE3-70) on the TRB for example ADCs or other devices. Then we have the TDC and ADC data all available in one FPGA and in total a board with 128 channels.
Line: 53 to 43
  The idea is to use the lower 80 pins exactly as used on the TRBv2 to be able to use the TRBv2 in the existing setups. (A small adapter board to the KEL-connectors has to be built for that). On the other hand, these connectors allow to build small AddOns which have the additional possibility to connect to 128 more pins (+ power). This allows to read out with the FPGA (LFE3-70) on the TRB for example ADCs or other devices. Then we have the TDC and ADC data all available in one FPGA and in total a board with 128 channels. Application: ECal for example.
Added:
>
>
  The pinout of the remaining 128 pins has to be chosen carefully (to be done).
Added:
>
>
Please help!
  http://www.samtec.com/documents/webfiles/pdf/qms.pdf
Changed:
<
<
- Standard reference time input: This then is fed to a fan-out chip, which will be fed to the FPGAs (twice as Marek said). And a RJ45 as secondary reference time input. (The input of the fanout-chips can select between two inputs. This can be done via a jumper.)
>
>
  • Standard reference time input: This then is fed to a fan-out chip, which will be fed to the FPGAs (twice as Marek said). And a RJ45 as secondary reference time input. (The input of the fanout-chips can select between two inputs. This can be done via a jumper.)
 
Changed:
<
<
- Additional auxilary connectors, like RJ45 + a normal pitch pin-header, all connected to the central FPGA. - Many LEDs! (Please label them LED1..8, not dgood, dwait etc.) maybe 4 for each FPGA.
>
>
  • Additional auxilary connectors, like RJ45 + a normal pitch pin-header, all connected to the central FPGA. *Many LEDs! (Please label them LED1..8, not dgood, dwait etc.) maybe 4 for each FPGA.
  And a test connector for each of the 4 FPGAs.
Changed:
<
<
Connection between FPGA: - SERDES connections - Each of the TDC-FPGAs has two SERDES connections to the central FPGA, coming from two QUADS. If possible, put one line of one quad to the mini-addon-connector. Put a set of 12 LVCMOS25 lines between the central FPGA and each of the other FPGAs
>
>

Connection between FPGA:

  • SERDES connections
  • Each of the TDC-FPGAs has two SERDES connections to the central FPGA, coming from two QUADS. If possible, put one line of one quad to the mini-addon-connector. Put a set of 12 LVCMOS25 lines between the central FPGA and each of the other FPGAs
  All 4 FPGAs have identical schematics and layout!
Added:
>
>
  - Each FPGA gets a FLASH to boot from. From the MDC-Hub2 we learned: Connect the programming lines from all flashs to the central FPGA - this way a broken Flash can be restored since the central FPGA is not affected by an upgrade of the other four FPGA. (There is no nice way to recover the central FPGA, but this one will be upgraded much more seldomly). (see comments) - JTAG chain.
Line: 76 to 65
  - JTAG chain.

- DDR2-3 RAM and SRAM I would skip on the 4 FPGAs, I don't see the obvious application.
Changed:
<
<
- Maybe an SRAM on the central FPGA. DDR3 is tricky!
>
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- Maybe an SRAM on the central FPGA. DDR3 is tricky and not !
  After reading TN1180 I would rather avoid DDR unless we really need it. If we need it we have to write vhdl code with proper constraints and without any drc errors before pin assignment. (Which is the usual way how to design boards in general...)
 
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