Difference: TRBAddOns (1 vs. 22)

Revision 22
27 Oct 2009 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoardV2"
Line: 72 to 72
 
META FILEATTACHMENT attr="" comment="GP-AddOn back" date="1185393082" name="gp_addon_back.jpg" path="gp_addon_back.jpg" size="2440070" user="AttilioTarantola" version="1.1"
META FILEATTACHMENT attr="" comment="TRB-HUB1" date="1193142598" name="TRB_HUB1.jpg" path="TRB_HUB1.jpg" size="2526610" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="TRB_HUB1 (small)" date="1193142894" name="TRB_HUB1_small.jpg" path="TRB_HUB1_small.jpg" size="66135" user="MichaelTraxler" version="1.1"
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META TOPICMOVED by="JanMichel" date="1256641613" from="DaqSlowControl.TDCReadoutBoardV2AddOn" to="DaqSlowControl.TRBAddOns"
Revision 21
05 Feb 2008 - Main.MichaelTraxler
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoardV2"
Line: 36 to 36
 

FPGA: LFE2-70E-5F900C from Lattice
Changed:
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Up to now (2007-09-13), a schematics is existing.
>
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Schematics are finished, layout is finished, we are waiting for the PCB (2008-02-05).
 

The General Purpose Add on: Short Description

The General Purpose Add on (GP-AddOn) board povides the interface between the TRBv2 (main readout board) and many different signals.
Revision 20
23 Oct 2007 - Main.MichaelTraxler
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoardV2"

Here we describe our various AddOn Cards for the TRBv2

Added:
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HUB-AddOn

The TRB-HUB servers as the trigger fanout-module.
It has 16 times a 2-GBit/s SFP. The SERDESes are in the LatticeSCM40 FPGA.
Fully impedance matched 12-layer PCB.

TRB_HUB1 (small)
 

ShowerAddOn

Line: 49 to 57
  General Purpose addon board: block diagram
GPAddon
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Connector A (JADDON1)

With these connectors (JADDON1 and JADDON2) the Add-on board communicates with the TRBv2 board: it receives trigger information and basically it sends data to TRBv2. In this connector we use ONLY LVDS signals between addon-board and TRB.

Pin Name Pos/Neg Direction
1 ADO_LV0 P I/O
2 ADO_LV28 P I/O
3 ADO_LV1 N I/O
4 ADO_LV29 N I/O
5 GND  
6 GND  
7 ADO_LV2 P I/O
8 ADO_LV30 P I/O
9 ADO_LV3 N I/O
10 ADO_LV31 N I/O
11 GND  
12 GND  
13 ADO_LV4 P I/O
14 ADO_LV32 P I/O
15 ADO_LV5 N I/O
16 ADO_LV33 N I/O
17 GND  
18 GND  
19 ADO_LV6 P I/O
20 ADO_LV34 P I/O
21 ADO_LV7 N I/O
22 ADO_LV35 N I/O
23 GND  
24 GND  
25 ADO_LV8 P I/O
26 ADO_LV36 P I/O
27 ADO_LV9 N I/O
28 ADO_LV37 N I/O
29 GND  
30 GND  
31 ADO_LV10 P I/O
32 ADO_LV38 P I/O
33 ADO_LV11 N I/O
34 ADO_LV39 N I/O
35 GND  
36 GND  
37 ADO_LV12 P I/O
38 ADO_LV40 P I/O
39 ADO_LV13 N I/O
40 ADO_LV41 N I/O
     
P1 5 V  
P2 5 V  
P3 5 V  
P4 5 V  
     
41 ADO_LV14 P I/O
42 ADO_LV42 P I/O
43 ADO_LV15 N I/O
44 ADO_LV43 N I/O
45 GND  
46 GND  
47 ADO_LV16 P I/O
48 ADO_LV44 P I/O
49 ADO_LV17 N I/O
50 ADO_LV45 N I/O
51 GND  
52 GND  
53 ADO_LV18 P I/O
54 ADO_LV46 P I/O
55 ADO_LV19 N I/O
56 ADO_LV47 N I/O
57 GND  
58 GND  
59 ADO_LV20 P I/O
60 ADO_LV48 P I/O
61 ADO_LV21 N I/O
62 ADO_LV49 N I/O
63 GND  
64 GND  
65 ADO_LV22 P I/O
66 ADO_LV50 P I/O
67 ADO_LV23 N I/O
68 ADO_LV51 N I/O
69 GND  
70 GND  
71 ADO_LV24 P I/O
72 ADO_LV52 P I/O
73 ADO_LV25 N I/O
74 ADO_LV53 N I/O
75 GND  
76 GND  
77 ADO_LV26 P I/O
78 ADO_LV54 P I/O
79 ADO_LV27 N I/O
80 ADO_LV55 N I/O
     
P5 GND  
P6 GND  
P7 GND  
P8 GND  

IN/OUT - direction seen from add-on board

Connector B (JADDON2)

Pin Name Comments
1 ADO_TTL0 LVTTL I/O
2 ADO_TTL20 LVTTL I/O
3 ADO_TTL1 LVTTL I/O
4 ADO_TTL21 LVTTL I/O
5 ADO_TTL2 LVTTL I/O
6 ADO_TTL22 LVTTL I/O
7 ADO_TTL3 LVTTL I/O
8 ADO_TTL23 LVTTL I/O
9 ADO_TTL4 LVTTL I/O
10 ADO_TTL24 LVTTL I/O
11 ADO_TTL5 LVTTL I/O
12 ADO_TTL25 LVTTL I/O
13 ADO_TTL6 LVTTL I/O
14 ADO_TTL26 LVTTL I/O
15 ADO_TTL7 LVTTL I/O
16 ADO_TTL27 LVTTL I/O
17 ADO_TTL8 LVTTL I/O
18 ADO_TTL28 LVTTL I/O
19 ADO_TTL9 LVTTL I/O
20 ADO_TTL29 LVTTL I/O
21 ADO_TTL10 LVTTL I/O
22 ADO_TTL30 LVTTL I/O
23 ADO_TTL11 LVTTL I/O
24 ADO_TTL31 LVTTL I/O
25 ADO_TTL12 LVTTL I/O
26 ADO_TTL32 LVTTL I/O
27 ADO_TTL13 LVTTL I/O
28 ADO_TTL33 LVTTL I/O
29 ADO_TTL14 LVTTL I/O
30 ADO_TTL34 LVTTL I/O
31 ADO_TTL15 LVTTL I/O
32 ADO_TTL35 LVTTL I/O
33 ADO_TTL16 LVTTL I/O
34 ADO_TTL36 LVTTL I/O
35 ADO_TTL17 LVTTL I/O
36 ADO_TTL37 LVTTL I/O
37 ADO_TTL18 LVTTL I/O
38 ADO_TTL38 LVTTL I/O
39 ADO_TTL19 LVTTL I/O
40 ADO_TTL39 LVTTL I/O
     
P1 5 V  
P2 5 V  
P3 5 V  
P4 5 V  
     
41 ADO_TTL42 LVTTL I/O
42 ADO_TTL40 LVTTL I/O
43 ADO_TTL43 LVTTL I/O TDO
44 ADO_TTL41 LVTTL I/O
45 ADO_TTL44 LVTTL I/O TCK
46 FS_PE0 LVTTL I/O
47 ADO_TTL45 LVTTL I/O TDI
48 FS_PE1 LVTTL I/O
49 ADO_TTL46 LVTTL I/O TMS
50 FS_PE2 LVTTL I/O
51 ADDON_RESET LVTTL IN
52 FS_PE3 LVTTL I/O
53 GND  
54 FS_PE4 LVTTL I/O
55 GND  
56 FS_PE5 LVTTL I/O
57 ADO_LV56 LVDS P I/O
58 FS_PE6 LVTTL I/O
59 ADO_LV57 LVDS N I/O
60 FS_PE7 LVTTL I/O
61 GND  
62 FS_PE8 LVTTL I/O
63 ADO_LV58 LVDS P OUT
64 FS_PE9 LVTTL I/O
65 ADO_LV59 LVDS N OUT
66 FS_PE10 LVTTL I/O
67 GND  
68 FS_PE11 LVTTL I/O
69 ADO_CLKOUT LVDS P OUT
70 FS_PE12 LVTTL I/O
71 ADO_CLKOUT LVDS N OUT
72 FS_PE13 LVTTL I/O
73 GND  
74 FS_PE14 LVTTL I/O
75 ADON_CLK LVDS P IN
76 FS_PE15 LVTTL I/O
77 ADON_CLK LVDS P IN
78 FS_PE16 LVTTL I/O
79 GND  
80 FS_PE17 LVTTL I/O
     
P5 GND  
P6 GND  
P7 GND  
P8 GND  

IN/OUT - direction seen from add-on board

Trb-Net media naming convention

The 31 GP LVDS lines plus the CLK line (only input in the Virtex4) will be the LVDS media for the NewTriggerBus. To avoid confusion, the assignment is given in this table:
LVDS pair on the schematics Official Name Direction
ADO_LVDS0,1 LVDS0 TRB to Acromag
...
ADO_LVDS30,31 LVDS15 TRB to Acromag
ADO_LVDS32,33 LVDS16 Acromag to TRB
ADO_LVDS34,35 LVDS17 Acromag to TRB
ADO_LVDS36,37 LVDS18 Acromag to TRB
ADO_LVDS38,39 LVDS19 Acromag to TRB
ADO_CLKOUT(p) LVDS20 Acromag to TRB
ADO_LVDS40,41 LVDS21 Acromag to TRB
...
ADO_LVDS60,61 LVDS31 Acromag to TRB

MDC Add-on Board: ERNI Connector(LVL1 bus)

With these connectors the MDC Add-on board communicates with the Motherboards placed on the MDC frame: it configures the TDCs on the Motherboards (through the CPLDs) and collects data.

Pin Name Direction Comment
1 TDZ   JTAG
2 TDA   JTAG
3 TMS   JTAG
4 TCK   JTAG
5 RES Out Mode device reset
6 TOK Out Mode token
7 MOD Out Mode select
8 WRM Out Mode-Write
9 GDE+ Out GDE+ Inhibit(global disable)
10 GDE- Out GDE- Inhibit(global disable)
11 AOD+ I/O Address or Data
12 AOD- I/O Address or Data
13 RDO+ In Ready from last Hamot
14 RDO- In Ready from last Hamot
15 CMS+ Out Common Stop output
16 CMS- Out Common Stop output
17 DST+ I/O Data Strobe I/O
18 DST- I/O Data Strobe I/O
19 ACK+ I/O Acknowledge
20 ACK- I/O Acknowledge
21 ADSO In Board Address input
22 NCO ??? Spare
23 ADS1 In Board Address input
24 NC1 ??? Spare
25 ADS2 In not used
26 NC2 ??? Spare
27 OR+ In Common Or input
28 OR- In Common Or input
29 RDM+ Out Ready to first Hamot
30 RDM- Out Ready to first Hamot
31 AD 00+ I/O Address/Data
32 AD 00- I/O Address/Data
33 AD 01+ I/O Address/Data
34 AD 01- I/O Address/Data
35 AD 02+ I/O Address/Data
36 AD 02- I/O Address/Data
37 AD 03+ I/O Address/Data
38 AD 03- I/O Address/Data
39 AD 04+ I/O Address/Data
40 AD 04- I/O Address/Data
41 AD 05+ I/O Address/Data
42 AD 05- I/O Address/Data
43 AD 06+ I/O Address/Data
44 AD 06- I/O Address/Data
45 AD 07+ I/O Address/Data
46 AD 07- I/O Address/Data
47 AD 08+ I/O Address/Data
48 AD 08- I/O Address/Data
49 RSV+ ??? (I/O) reserve
50 RSV- ??? (I/O) reserve

IN/OUT - direction seen from add-on board

Pinout of the transceivers placed on the ROC board:

Two of 75976A2 transceivers are connected to one ERNI connector. In the first row there are the enable signals (6) and in the column the name of the corresponding pins.

REN ENR   ENB   DRB   DRA   DRE
RSV GDE   AOD   RDO   ACK   AD01
  RDM   DST   OR       AD02
  CMS               AD03
                AD04
                AD05
                AD06
                AD07
                AD08
                AD09
 
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Pinouts and connectors

 
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-- AttilioTarantola - 09 Oct 2006
 
Deleted:
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-- AttilioTarantola - 09 Oct 2006
 

META FILEATTACHMENT attr="" comment="General purpose addon board" date="1184331387" name="gp_addon_front.jpg" path="gp_addon_front.jpg" size="2491317" user="AttilioTarantola" version="1.1"
META FILEATTACHMENT attr="" comment="general porpouse addon block diagram" date="1185205638" name="general_porpouse_addon.gif" path="general_porpouse_addon.gif" size="57879" user="AttilioTarantola" version="1.1"
META FILEATTACHMENT attr="" comment="GP-AddOn back" date="1185393082" name="gp_addon_back.jpg" path="gp_addon_back.jpg" size="2440070" user="AttilioTarantola" version="1.1"
Added:
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META FILEATTACHMENT attr="" comment="TRB-HUB1" date="1193142598" name="TRB_HUB1.jpg" path="TRB_HUB1.jpg" size="2526610" user="MichaelTraxler" version="1.1"
META FILEATTACHMENT attr="" comment="TRB_HUB1 (small)" date="1193142894" name="TRB_HUB1_small.jpg" path="TRB_HUB1_small.jpg" size="66135" user="MichaelTraxler" version="1.1"
Revision 19
13 Sep 2007 - Main.MichaelTraxler
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoardV2"
Changed:
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The General Purpose Add on: Short Description

>
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Here we describe our various AddOn Cards for the TRBv2

ShowerAddOn

The features of the ShowerAddOn alias General-Purpose-ADC-AddOn

  • 96 channels 10-bit ADCs
  • 40/60 MSPS
  • ADC type: AD9212 from Analog Devices
  • low noise, variable gain amplifier at the input (AD8334 from Analog Devices)
  • input voltage range: ± 275 mV (AC coupled),
  • -3 dB bandwidth: 100 MHz (independent on gain)
  • amplifier noise: 0.74 nV/sqrt(Hz), 2.5 pA/sqrt(Hz)

  • Two 68-pin connectors, each connector contains:
    • 48 analog inputs,
    • 5 LVDS lines (programmable direction)
    • 2 TTL lines (programmable direction)
    • +5V (2 pins), GND (6 pins).
    • Connector type: HDRA-EC68LFDT-SL from Honda Connectors

FPGA: LFE2-70E-5F900C from Lattice

Up to now (2007-09-13), a schematics is existing.

The General Purpose Add on: Short Description

  The General Purpose Add on (GP-AddOn) board povides the interface between the TRBv2 (main readout board) and many different signals. For example it can used as interface to the old HADES trigger bus. The GP-AddOn can be easily connected to the TRBv2 board through 2 connectors (QSE-040-01) placed on the back side of the board. The power supply is given to the GP-Addon through the connector's pins.
Line: 19 to 49
  General Purpose addon board: block diagram
GPAddon
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Connector A (JADDON1)

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Connector A (JADDON1)

 

With these connectors (JADDON1 and JADDON2) the Add-on board communicates with the TRBv2 board: it receives trigger information and basically it sends data to TRBv2. In this connector we use ONLY LVDS signals between addon-board and TRB.
Line: 120 to 150
 

IN/OUT - direction seen from add-on board
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Connector B (JADDON2)

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Connector B (JADDON2)

 

Pin Name Comments
1 ADO_TTL0 LVTTL I/O
Line: 218 to 248
 

IN/OUT - direction seen from add-on board
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Trb-Net media naming convention

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Trb-Net media naming convention

 

The 31 GP LVDS lines plus the CLK line (only input in the Virtex4) will be the LVDS media for the NewTriggerBus. To avoid confusion, the assignment is given in this table:
LVDS pair on the schematics Official Name Direction
Line: 234 to 264
 
...
ADO_LVDS60,61 LVDS31 Acromag to TRB
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MDC Add-on Board: ERNI Connector(LVL1 bus)

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MDC Add-on Board: ERNI Connector(LVL1 bus)

 

With these connectors the MDC Add-on board communicates with the Motherboards placed on the MDC frame: it configures the TDCs on the Motherboards (through the CPLDs) and collects data.
Line: 293 to 323
 

IN/OUT - direction seen from add-on board
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Pinout of the transceivers placed on the ROC board:

>
>

Pinout of the transceivers placed on the ROC board:

 

Two of 75976A2 transceivers are connected to one ERNI connector. In the first row there are the enable signals (6) and in the column the name of the corresponding pins.
Revision 18
16 Aug 2007 - Main.AttilioTarantola
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoardV2"

The General Purpose Add on: Short Description

The General Purpose Add on (GP-AddOn) board povides the interface between the TRBv2 (main readout board) and many different signals.
Line: 9 to 9
  functional and timing simulation. Here we attach the data sheets for further details of the board's component:
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.components data sheet.. ..work in progress...
 
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* General Purpose addon board.:
>
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General Purpose addon board: front view
  GPAddon
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* General Purpose addon board.:
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General Purpose addon board: back view
  GPAddon
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* General Purpose addon board: block diagram:
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General Purpose addon board: block diagram
  GPAddon

Connector A (JADDON1)

Revision 17
25 Jul 2007 - Main.AttilioTarantola
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoardV2"
Changed:
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Short Description (..)

--block diagram --picture... ..components data sheet..
>
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The General Purpose Add on: Short Description

The General Purpose Add on (GP-AddOn) board povides the interface between the TRBv2 (main readout board) and many different signals. For example it can used as interface to the old HADES trigger bus. The GP-AddOn can be easily connected to the TRBv2 board through 2 connectors (QSE-040-01) placed on the back side of the board. The power supply is given to the GP-Addon through the connector's pins. A programmable logic CPLD ( XCR3128XL7VQ100C) is placed on the right hand side and is supported by Xilinx Web-PACK™ and industry standard CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor, Synopsys, Viewlogic, and Synplicity), using HDL editors with ABEL, VHDL, and Verilog. Design verification uses industry standard simulators for functional and timing simulation. Here we attach the data sheets for further details of the board's component:

.components data sheet..
  ..work in progress...
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  * General Purpose addon board.:
GPAddon
Line: 8 to 15
  * General Purpose addon board.:
GPAddon
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* General Purpose addon board.:
GPAddon
  * General Purpose addon board: block diagram:
GPAddon
Line: 309 to 319
 

META FILEATTACHMENT attr="" comment="General purpose addon board" date="1184331387" name="gp_addon_front.jpg" path="gp_addon_front.jpg" size="2491317" user="AttilioTarantola" version="1.1"
META FILEATTACHMENT attr="" comment="general porpouse addon block diagram" date="1185205638" name="general_porpouse_addon.gif" path="general_porpouse_addon.gif" size="57879" user="AttilioTarantola" version="1.1"
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META FILEATTACHMENT attr="" comment="GP-AddOn back" date="1185393082" name="gp_addon_back.jpg" path="gp_addon_back.jpg" size="2440070" user="AttilioTarantola" version="1.1"
Revision 16
23 Jul 2007 - Main.AttilioTarantola
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoardV2"

Short Description (..)

--block diagram
Line: 8 to 8
  * General Purpose addon board.:
GPAddon
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* General Purpose addon board: block diagram:
GPAddon
 

Connector A (JADDON1)

With these connectors (JADDON1 and JADDON2) the Add-on board communicates with the TRBv2 board: it receives trigger information and basically it sends data to TRBv2.
Line: 223 to 226
 
...
ADO_LVDS60,61 LVDS31 Acromag to TRB
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Connector(Erni) Add-on board/Motherboard

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MDC Add-on Board: ERNI Connector(LVL1 bus)

 
Changed:
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With these connectors the Add-on board communicates with the Motherboards: it configures the TDCs on the Motherboards (through the CPLDs) and collects data.
>
>
With these connectors the MDC Add-on board communicates with the Motherboards placed on the MDC frame: it configures the TDCs on the Motherboards (through the CPLDs) and collects data.
 

Pin Name Direction Comment
1 TDZ   JTAG
Line: 305 to 308
  -- AttilioTarantola - 09 Oct 2006

META FILEATTACHMENT attr="" comment="General purpose addon board" date="1184331387" name="gp_addon_front.jpg" path="gp_addon_front.jpg" size="2491317" user="AttilioTarantola" version="1.1"
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META FILEATTACHMENT attr="" comment="general porpouse addon block diagram" date="1185205638" name="general_porpouse_addon.gif" path="general_porpouse_addon.gif" size="57879" user="AttilioTarantola" version="1.1"
Revision 15
13 Jul 2007 - Main.AttilioTarantola
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoardV2"

Short Description (..)

--block diagram --picture... ..components data sheet..
Added:
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..work in progress... * General Purpose addon board.:
GPAddon
 

Connector A (JADDON1)

Line: 301 to 304
 

-- AttilioTarantola - 09 Oct 2006
Added:
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META FILEATTACHMENT attr="" comment="General purpose addon board" date="1184331387" name="gp_addon_front.jpg" path="gp_addon_front.jpg" size="2491317" user="AttilioTarantola" version="1.1"
Revision 14
10 Jul 2007 - Main.AttilioTarantola
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoardV2"
Added:
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Short Description (..)

--block diagram --picture... ..components data sheet..
 

Connector A (JADDON1)

With these connectors (JADDON1 and JADDON2) the Add-on board communicates with the TRBv2 board: it receives trigger information and basically it sends data to TRBv2.
Revision 13
02 May 2007 - Main.MichaelTraxler
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoardV2"

Connector A (JADDON1)

Revision 12
31 Oct 2006 - Main.AttilioTarantola
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoardV2"

Connector A (JADDON1)

Line: 240 to 240
 
18 DST- I/O Data Strobe I/O
19 ACK+ I/O Acknowledge
20 ACK- I/O Acknowledge
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21 ADSO ??? Board Address input
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21 ADSO In Board Address input
 
22 NCO ??? Spare
Changed:
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23 ADS1 ??? Board Address input
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23 ADS1 In Board Address input
 
24 NC1 ??? Spare
Changed:
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25 not connected - -
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25 ADS2 In not used
 
26 NC2 ??? Spare
27 OR+ In Common Or input
28 OR- In Common Or input
Line: 268 to 268
 
46 AD 07- I/O Address/Data
47 AD 08+ I/O Address/Data
48 AD 08- I/O Address/Data
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49 RSV+ ??? reserve
50 RSV- ??? reserve
>
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49 RSV+ ??? (I/O) reserve
50 RSV- ??? (I/O) reserve
 

IN/OUT - direction seen from add-on board
Revision 11
18 Oct 2006 - Main.IngoFroehlich
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoardV2"

Connector A (JADDON1)

Line: 199 to 199
 

IN/OUT - direction seen from add-on board
Added:
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Trb-Net media naming convention

The 31 GP LVDS lines plus the CLK line (only input in the Virtex4) will be the LVDS media for the NewTriggerBus. To avoid confusion, the assignment is given in this table:
LVDS pair on the schematics Official Name Direction
ADO_LVDS0,1 LVDS0 TRB to Acromag
...
ADO_LVDS30,31 LVDS15 TRB to Acromag
ADO_LVDS32,33 LVDS16 Acromag to TRB
ADO_LVDS34,35 LVDS17 Acromag to TRB
ADO_LVDS36,37 LVDS18 Acromag to TRB
ADO_LVDS38,39 LVDS19 Acromag to TRB
ADO_CLKOUT(p) LVDS20 Acromag to TRB
ADO_LVDS40,41 LVDS21 Acromag to TRB
...
ADO_LVDS60,61 LVDS31 Acromag to TRB
 

Connector(Erni) Add-on board/Motherboard

Revision 10
09 Oct 2006 - Main.AttilioTarantola
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoardV2"

Connector A (JADDON1)

Line: 259 to 259
 

IN/OUT - direction seen from add-on board
Changed:
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<
-- AttilioTarantola - 06 Oct 2006
>
>

Pinout of the transceivers placed on the ROC board:

Two of 75976A2 transceivers are connected to one ERNI connector. In the first row there are the enable signals (6) and in the column the name of the corresponding pins.

REN ENR   ENB   DRB   DRA   DRE
RSV GDE   AOD   RDO   ACK   AD01
  RDM   DST   OR       AD02
  CMS               AD03
                AD04
                AD05
                AD06
                AD07
                AD08
                AD09

-- AttilioTarantola - 09 Oct 2006
 
Revision 9
06 Oct 2006 - Main.AttilioTarantola
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoardV2"

Connector A (JADDON1)

Deleted:
<
<
In this connector we use ONLY LVDS signals between addon-board and TRB
 
Added:
>
>
With these connectors (JADDON1 and JADDON2) the Add-on board communicates with the TRBv2 board: it receives trigger information and basically it sends data to TRBv2. In this connector we use ONLY LVDS signals between addon-board and TRB.
 

Pin Name Pos/Neg Direction
1 ADO_LV0 P I/O
Line: 198 to 199
 

IN/OUT - direction seen from add-on board
Changed:
<
<
-- AttilioTarantola - 04 Oct 2006
>
>

Connector(Erni) Add-on board/Motherboard

With these connectors the Add-on board communicates with the Motherboards: it configures the TDCs on the Motherboards (through the CPLDs) and collects data.

Pin Name Direction Comment
1 TDZ   JTAG
2 TDA   JTAG
3 TMS   JTAG
4 TCK   JTAG
5 RES Out Mode device reset
6 TOK Out Mode token
7 MOD Out Mode select
8 WRM Out Mode-Write
9 GDE+ Out GDE+ Inhibit(global disable)
10 GDE- Out GDE- Inhibit(global disable)
11 AOD+ I/O Address or Data
12 AOD- I/O Address or Data
13 RDO+ In Ready from last Hamot
14 RDO- In Ready from last Hamot
15 CMS+ Out Common Stop output
16 CMS- Out Common Stop output
17 DST+ I/O Data Strobe I/O
18 DST- I/O Data Strobe I/O
19 ACK+ I/O Acknowledge
20 ACK- I/O Acknowledge
21 ADSO ??? Board Address input
22 NCO ??? Spare
23 ADS1 ??? Board Address input
24 NC1 ??? Spare
25 not connected - -
26 NC2 ??? Spare
27 OR+ In Common Or input
28 OR- In Common Or input
29 RDM+ Out Ready to first Hamot
30 RDM- Out Ready to first Hamot
31 AD 00+ I/O Address/Data
32 AD 00- I/O Address/Data
33 AD 01+ I/O Address/Data
34 AD 01- I/O Address/Data
35 AD 02+ I/O Address/Data
36 AD 02- I/O Address/Data
37 AD 03+ I/O Address/Data
38 AD 03- I/O Address/Data
39 AD 04+ I/O Address/Data
40 AD 04- I/O Address/Data
41 AD 05+ I/O Address/Data
42 AD 05- I/O Address/Data
43 AD 06+ I/O Address/Data
44 AD 06- I/O Address/Data
45 AD 07+ I/O Address/Data
46 AD 07- I/O Address/Data
47 AD 08+ I/O Address/Data
48 AD 08- I/O Address/Data
49 RSV+ ??? reserve
50 RSV- ??? reserve

IN/OUT - direction seen from add-on board

-- AttilioTarantola - 06 Oct 2006
 
Revision 8
06 Oct 2006 - Main.AttilioTarantola
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoardV2"

Connector A (JADDON1)

In this connector we use ONLY LVDS signals between addon-board and TRB
Line: 98 to 98
 
P8 GND  
Changed:
<
<
>
>
IN/OUT - direction seen from add-on board
 

Connector B (JADDON2)

Line: 196 to 196
 
P8 GND  
Added:
>
>
IN/OUT - direction seen from add-on board
  -- AttilioTarantola - 04 Oct 2006
Revision 7
04 Oct 2006 - Main.AttilioTarantola
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoardV2"

Connector A (JADDON1)

In this connector we use ONLY LVDS signals between addon-board and TRB
Changed:
<
<
Pin Name Comments
1 ADO_LV0  
2 ADO_LV28  
3 ADO_LV1  
4 ADO_LV29  
>
>
Pin Name Pos/Neg Direction
1 ADO_LV0 P I/O
2 ADO_LV28 P I/O
3 ADO_LV1 N I/O
4 ADO_LV29 N I/O
 
5 GND  
6 GND  
Changed:
<
<
7 ADO_LV2  
8 ADO_LV30  
9 ADO_LV3  
10 ADO_LV31  
>
>
7 ADO_LV2 P I/O
8 ADO_LV30 P I/O
9 ADO_LV3 N I/O
10 ADO_LV31 N I/O
 
11 GND  
12 GND  
Changed:
<
<
13 ADO_LV4  
14 ADO_LV32  
15 ADO_LV5  
16 ADO_LV33  
>
>
13 ADO_LV4 P I/O
14 ADO_LV32 P I/O
15 ADO_LV5 N I/O
16 ADO_LV33 N I/O
 
17 GND  
18 GND  
Changed:
<
<
19 ADO_LV6  
20 ADO_LV34  
21 ADO_LV7  
22 ADO_LV35  
>
>
19 ADO_LV6 P I/O
20 ADO_LV34 P I/O
21 ADO_LV7 N I/O
22 ADO_LV35 N I/O
 
23 GND  
24 GND  
Changed:
<
<
25 ADO_LV8  
26 ADO_LV36  
27 ADO_LV9  
28 ADO_LV37  
>
>
25 ADO_LV8 P I/O
26 ADO_LV36 P I/O
27 ADO_LV9 N I/O
28 ADO_LV37 N I/O
 
29 GND  
30 GND  
Changed:
<
<
31 ADO_LV10  
32 ADO_LV38  
33 ADO_LV11  
34 ADO_LV39  
>
>
31 ADO_LV10 P I/O
32 ADO_LV38 P I/O
33 ADO_LV11 N I/O
34 ADO_LV39 N I/O
 
35 GND  
36 GND  
Changed:
<
<
37 ADO_LV12  
38 ADO_LV40  
39 ADO_LV13  
40 ADO_LV41  
>
>
37 ADO_LV12 P I/O
38 ADO_LV40 P I/O
39 ADO_LV13 N I/O
40 ADO_LV41 N I/O
 
     
P1 5 V  
P2 5 V  
P3 5 V  
P4 5 V  
     
Changed:
<
<
     
     
41 ADO_LV14  
42 ADO_LV42  
43 ADO_LV15  
44 ADO_LV43  
>
>
41 ADO_LV14 P I/O
42 ADO_LV42 P I/O
43 ADO_LV15 N I/O
44 ADO_LV43 N I/O
 
45 GND  
46 GND  
Changed:
<
<
47 ADO_LV16  
48 ADO_LV44  
49 ADO_LV17  
50 ADO_LV45  
>
>
47 ADO_LV16 P I/O
48 ADO_LV44 P I/O
49 ADO_LV17 N I/O
50 ADO_LV45 N I/O
 
51 GND  
52 GND  
Changed:
<
<
53 ADO_LV18  
54 ADO_LV46  
55 ADO_LV19  
56 ADO_LV47  
>
>
53 ADO_LV18 P I/O
54 ADO_LV46 P I/O
55 ADO_LV19 N I/O
56 ADO_LV47 N I/O
 
57 GND  
58 GND  
Changed:
<
<
59 ADO_LV20  
60 ADO_LV48  
61 ADO_LV21  
62 ADO_LV49  
>
>
59 ADO_LV20 P I/O
60 ADO_LV48 P I/O
61 ADO_LV21 N I/O
62 ADO_LV49 N I/O
 
63 GND  
64 GND  
Changed:
<
<
65 ADO_LV22  
66 ADO_LV50  
67 ADO_LV23  
68 ADO_LV51  
>
>
65 ADO_LV22 P I/O
66 ADO_LV50 P I/O
67 ADO_LV23 N I/O
68 ADO_LV51 N I/O
 
69 GND  
70 GND  
Changed:
<
<
71 ADO_LV24  
72 ADO_LV52  
73 ADO_LV25  
74 ADO_LV53  
>
>
71 ADO_LV24 P I/O
72 ADO_LV52 P I/O
73 ADO_LV25 N I/O
74 ADO_LV53 N I/O
 
75 GND  
76 GND  
Changed:
<
<
77 ADO_LV26  
78 ADO_LV54  
79 ADO_LV27  
80 ADO_LV55  
>
>
77 ADO_LV26 P I/O
78 ADO_LV54 P I/O
79 ADO_LV27 N I/O
80 ADO_LV55 N I/O
 
     
P5 GND  
P6 GND  
Line: 103 to 101
 

Connector B (JADDON2)

Added:
>
>
 
Pin Name Comments
Changed:
<
<
1 ADO_TTL0  
2 ADO_TTL19  
3 ADO_TTL1  
4 ADO_TTL20  
5 ADO_TTL2  
6 ADO_TTL21  
7 ADO_TTL3  
8 ADO_TTL22  
9 ADO_TTL4  
10 ADO_TTL23  
11 ADO_TTL5  
12 ADO_TTL24  
13 ADO_TTL6  
14 ADO_TTL25  
15 ADO_TTL7  
16 ADO_TTL26  
17 ADO_TTL8  
18 ADO_TTL27  
19 ADO_TTL9  
20 ADO_TTL28  
21 ADO_TTL10  
22 GND  
23 ADO_TTL11  
24 GND  
25 ADO_TTL12  
26 ADO_LV80  
27 ADO_TTL13  
28 ADO_LV81  
29 ADO_TTL14  
30 GND  
31 ADO_TTL15  
32 ADO_LV82  
33 ADO_TTL16  
34 ADO_LV83  
35 ADO_TTL17  
36 GND  
37 ADO_TTL18  
38 ADO_LV84  
39 ADDON_RESET  
40 ADO_LV85  
>
>
1 ADO_TTL0 LVTTL I/O
2 ADO_TTL20 LVTTL I/O
3 ADO_TTL1 LVTTL I/O
4 ADO_TTL21 LVTTL I/O
5 ADO_TTL2 LVTTL I/O
6 ADO_TTL22 LVTTL I/O
7 ADO_TTL3 LVTTL I/O
8 ADO_TTL23 LVTTL I/O
9 ADO_TTL4 LVTTL I/O
10 ADO_TTL24 LVTTL I/O
11 ADO_TTL5 LVTTL I/O
12 ADO_TTL25 LVTTL I/O
13 ADO_TTL6 LVTTL I/O
14 ADO_TTL26 LVTTL I/O
15 ADO_TTL7 LVTTL I/O
16 ADO_TTL27 LVTTL I/O
17 ADO_TTL8 LVTTL I/O
18 ADO_TTL28 LVTTL I/O
19 ADO_TTL9 LVTTL I/O
20 ADO_TTL29 LVTTL I/O
21 ADO_TTL10 LVTTL I/O
22 ADO_TTL30 LVTTL I/O
23 ADO_TTL11 LVTTL I/O
24 ADO_TTL31 LVTTL I/O
25 ADO_TTL12 LVTTL I/O
26 ADO_TTL32 LVTTL I/O
27 ADO_TTL13 LVTTL I/O
28 ADO_TTL33 LVTTL I/O
29 ADO_TTL14 LVTTL I/O
30 ADO_TTL34 LVTTL I/O
31 ADO_TTL15 LVTTL I/O
32 ADO_TTL35 LVTTL I/O
33 ADO_TTL16 LVTTL I/O
34 ADO_TTL36 LVTTL I/O
35 ADO_TTL17 LVTTL I/O
36 ADO_TTL37 LVTTL I/O
37 ADO_TTL18 LVTTL I/O
38 ADO_TTL38 LVTTL I/O
39 ADO_TTL19 LVTTL I/O
40 ADO_TTL39 LVTTL I/O
 
     
P1 5 V  
P2 5 V  
P3 5 V  
P4 5 V  
     
Changed:
<
<
     
     
41 ADO_LV56  
42 ADO_LV68  
43 ADO_LV57  
44 ADO_LV69  
45 GND  
46 GND  
47 ADO_LV58  
48 ADO_LV70  
49 ADO_LV59  
50 ADO_LV71  
51 GND  
52 GND  
53 ADO_LV60  
54 ADO_LV72  
55 ADO_LV61  
56 ADO_LV73  
57 GND  
58 GND  
59 ADO_LV62  
60 ADO_LV74  
61 ADO_LV63  
62 ADO_LV75  
63 GND  
64 GND  
65 ADO_LV64  
66 ADO_LV76  
67 ADO_LV65  
68 ADO_LV77  
69 GND  
70 GND  
71 ADO_LV66  
72 ADO_LV78  
73 ADO_LV67  
74 ADO_LV79  
75 GND  
76 GND  
77 ADON_CLK  
78 ADO_CLKINP  
79 ADON_CLKb  
80 ADO_CLKINN  
>
>
41 ADO_TTL42 LVTTL I/O
42 ADO_TTL40 LVTTL I/O
43 ADO_TTL43 LVTTL I/O TDO
44 ADO_TTL41 LVTTL I/O
45 ADO_TTL44 LVTTL I/O TCK
46 FS_PE0 LVTTL I/O
47 ADO_TTL45 LVTTL I/O TDI
48 FS_PE1 LVTTL I/O
49 ADO_TTL46 LVTTL I/O TMS
50 FS_PE2 LVTTL I/O
51 ADDON_RESET LVTTL IN
52 FS_PE3 LVTTL I/O
53 GND  
54 FS_PE4 LVTTL I/O
55 GND  
56 FS_PE5 LVTTL I/O
57 ADO_LV56 LVDS P I/O
58 FS_PE6 LVTTL I/O
59 ADO_LV57 LVDS N I/O
60 FS_PE7 LVTTL I/O
61 GND  
62 FS_PE8 LVTTL I/O
63 ADO_LV58 LVDS P OUT
64 FS_PE9 LVTTL I/O
65 ADO_LV59 LVDS N OUT
66 FS_PE10 LVTTL I/O
67 GND  
68 FS_PE11 LVTTL I/O
69 ADO_CLKOUT LVDS P OUT
70 FS_PE12 LVTTL I/O
71 ADO_CLKOUT LVDS N OUT
72 FS_PE13 LVTTL I/O
73 GND  
74 FS_PE14 LVTTL I/O
75 ADON_CLK LVDS P IN
76 FS_PE15 LVTTL I/O
77 ADON_CLK LVDS P IN
78 FS_PE16 LVTTL I/O
79 GND  
80 FS_PE17 LVTTL I/O
 
     
P5 GND  
P6 GND  
Line: 199 to 196
 
P8 GND  
Changed:
<
<

-- AttilioTarantola - 26 Sep 2006
>
>
-- AttilioTarantola - 04 Oct 2006
 
Revision 6
26 Sep 2006 - Main.AttilioTarantola
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoardV2"

Connector A (JADDON1)

Changed:
<
<
In this connector we use LVDS signals addon-board/TRB
>
>
In this connector we use ONLY LVDS signals between addon-board and TRB
 
Changed:
<
<
Pin name Direction
>
>
Pin Name Comments
 
1 ADO_LV0  
2 ADO_LV28  
3 ADO_LV1  
Line: 54 to 53
 
     
     
     
Changed:
<
<

>
>
41 ADO_LV14  
42 ADO_LV42  
43 ADO_LV15  
44 ADO_LV43  
45 GND  
46 GND  
47 ADO_LV16  
48 ADO_LV44  
49 ADO_LV17  
50 ADO_LV45  
51 GND  
52 GND  
53 ADO_LV18  
54 ADO_LV46  
55 ADO_LV19  
56 ADO_LV47  
57 GND  
58 GND  
59 ADO_LV20  
60 ADO_LV48  
61 ADO_LV21  
62 ADO_LV49  
63 GND  
64 GND  
65 ADO_LV22  
66 ADO_LV50  
67 ADO_LV23  
68 ADO_LV51  
69 GND  
70 GND  
71 ADO_LV24  
72 ADO_LV52  
73 ADO_LV25  
74 ADO_LV53  
75 GND  
76 GND  
77 ADO_LV26  
78 ADO_LV54  
79 ADO_LV27  
80 ADO_LV55  
     
P5 GND  
P6 GND  
P7 GND  
P8 GND  
 

Connector B (JADDON2)

Added:
>
>
Pin Name Comments
1 ADO_TTL0  
2 ADO_TTL19  
3 ADO_TTL1  
4 ADO_TTL20  
5 ADO_TTL2  
6 ADO_TTL21  
7 ADO_TTL3  
8 ADO_TTL22  
9 ADO_TTL4  
10 ADO_TTL23  
11 ADO_TTL5  
12 ADO_TTL24  
13 ADO_TTL6  
14 ADO_TTL25  
15 ADO_TTL7  
16 ADO_TTL26  
17 ADO_TTL8  
18 ADO_TTL27  
19 ADO_TTL9  
20 ADO_TTL28  
21 ADO_TTL10  
22 GND  
23 ADO_TTL11  
24 GND  
25 ADO_TTL12  
26 ADO_LV80  
27 ADO_TTL13  
28 ADO_LV81  
29 ADO_TTL14  
30 GND  
31 ADO_TTL15  
32 ADO_LV82  
33 ADO_TTL16  
34 ADO_LV83  
35 ADO_TTL17  
36 GND  
37 ADO_TTL18  
38 ADO_LV84  
39 ADDON_RESET  
40 ADO_LV85  
     
P1 5 V  
P2 5 V  
P3 5 V  
P4 5 V  
     
     
     
41 ADO_LV56  
42 ADO_LV68  
43 ADO_LV57  
44 ADO_LV69  
45 GND  
46 GND  
47 ADO_LV58  
48 ADO_LV70  
49 ADO_LV59  
50 ADO_LV71  
51 GND  
52 GND  
53 ADO_LV60  
54 ADO_LV72  
55 ADO_LV61  
56 ADO_LV73  
57 GND  
58 GND  
59 ADO_LV62  
60 ADO_LV74  
61 ADO_LV63  
62 ADO_LV75  
63 GND  
64 GND  
65 ADO_LV64  
66 ADO_LV76  
67 ADO_LV65  
68 ADO_LV77  
69 GND  
70 GND  
71 ADO_LV66  
72 ADO_LV78  
73 ADO_LV67  
74 ADO_LV79  
75 GND  
76 GND  
77 ADON_CLK  
78 ADO_CLKINP  
79 ADON_CLKb  
80 ADO_CLKINN  
     
P5 GND  
P6 GND  
P7 GND  
P8 GND  
 
Deleted:
<
<
Pin Signal Polarity (if LVDS) Direction
2 LVDS pins CLK pos to add-on
2 LVDS pins RST pos to add-on
5 pins (no LVDS) JTAG - to add-on
70+1 LVDS pins general I/O (HTDC bus) pos to add-on/to trb
 

-- AttilioTarantola - 26 Sep 2006
Revision 5
26 Sep 2006 - Main.AttilioTarantola
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoardV2"

Connector A (JADDON1)

Added:
>
>
In this connector we use LVDS signals addon-board/TRB
 

Pin name Direction
1 ADO_LV0  
Changed:
<
<
2 ADO_LV1  
3 ADO_LV0  
4 ADO_LV0  
5 ADO_LV1  
6 ADO_LV0  
7 ADO_LV0  
8 ADO_LV1  
9 ADO_LV0  
10 ADO_LV0  
11 ADO_LV1  
12 ADO_LV0  
13 ADO_LV0  
14 ADO_LV1  
15 ADO_LV0  
16 ADO_LV0  
17 ADO_LV1  
18 ADO_LV0  
19 ADO_LV0  
20 ADO_LV1  
21 ADO_LV0  
22 ADO_LV0  
23 ADO_LV1  
24 ADO_LV0  
25 ADO_LV0  
26 ADO_LV1  
27 ADO_LV0  
28 ADO_LV0  
29 ADO_LV1  
30 ADO_LV0  
31 ADO_LV0  
32 ADO_LV1  
33 ADO_LV0  
34 ADO_LV0  
35 ADO_LV1  
36 ADO_LV0  
37 ADO_LV0  
38 ADO_LV1  
39 ADO_LV0  
40 ADO_LV0  
>
>
2 ADO_LV28  
3 ADO_LV1  
4 ADO_LV29  
5 GND  
6 GND  
7 ADO_LV2  
8 ADO_LV30  
9 ADO_LV3  
10 ADO_LV31  
11 GND  
12 GND  
13 ADO_LV4  
14 ADO_LV32  
15 ADO_LV5  
16 ADO_LV33  
17 GND  
18 GND  
19 ADO_LV6  
20 ADO_LV34  
21 ADO_LV7  
22 ADO_LV35  
23 GND  
24 GND  
25 ADO_LV8  
26 ADO_LV36  
27 ADO_LV9  
28 ADO_LV37  
29 GND  
30 GND  
31 ADO_LV10  
32 ADO_LV38  
33 ADO_LV11  
34 ADO_LV39  
35 GND  
36 GND  
37 ADO_LV12  
38 ADO_LV40  
39 ADO_LV13  
40 ADO_LV41  
     
 
P1 5 V  
P2 5 V  
P3 5 V  
P4 5 V  
Added:
>
>
     
     
     

 

Connector B (JADDON2)

Revision 4
26 Sep 2006 - Main.AttilioTarantola
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoardV2"

Connector A (JADDON1)

Pin name Direction
Changed:
<
<
24 data pos to trb
12 GND to trb
44 general I/O pos to add-on/to trb

>
>
1 ADO_LV0  
2 ADO_LV1  
3 ADO_LV0  
4 ADO_LV0  
5 ADO_LV1  
6 ADO_LV0  
7 ADO_LV0  
8 ADO_LV1  
9 ADO_LV0  
10 ADO_LV0  
11 ADO_LV1  
12 ADO_LV0  
13 ADO_LV0  
14 ADO_LV1  
15 ADO_LV0  
16 ADO_LV0  
17 ADO_LV1  
18 ADO_LV0  
19 ADO_LV0  
20 ADO_LV1  
21 ADO_LV0  
22 ADO_LV0  
23 ADO_LV1  
24 ADO_LV0  
25 ADO_LV0  
26 ADO_LV1  
27 ADO_LV0  
28 ADO_LV0  
29 ADO_LV1  
30 ADO_LV0  
31 ADO_LV0  
32 ADO_LV1  
33 ADO_LV0  
34 ADO_LV0  
35 ADO_LV1  
36 ADO_LV0  
37 ADO_LV0  
38 ADO_LV1  
39 ADO_LV0  
40 ADO_LV0  
P1 5 V  
P2 5 V  
P3 5 V  
P4 5 V  
 

Connector B (JADDON2)

Revision 3
26 Sep 2006 - Main.AttilioTarantola
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoardV2"
Changed:
<
<

Connector A

>
>

Connector A (JADDON1)

 
Changed:
<
<
Pin Signal Polarity (if LVDS) Direction
24 LVDS pins data pos to trb
12 LVDS pins GND - to trb
44 LVDS pins general I/O pos to add-on/to trb
>
>
Pin name Direction
24 data pos to trb
12 GND to trb
44 general I/O pos to add-on/to trb
 

Changed:
<
<

Connector B

>
>

Connector B (JADDON2)

 

Pin Signal Polarity (if LVDS) Direction
Line: 19 to 19
 
5 pins (no LVDS) JTAG - to add-on
70+1 LVDS pins general I/O (HTDC bus) pos to add-on/to trb
Changed:
<
<
-- IngoFroehlich - 05 Sep 2006
>
>

-- AttilioTarantola - 26 Sep 2006
 
Revision 2
05 Sep 2006 - Main.AttilioTarantola
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoardV2"
Deleted:
<
<
 

Connector A

Deleted:
<
<
Just a template...
 

Pin Signal Polarity (if LVDS) Direction
Changed:
<
<
1 data0 pos to add-on
2 data1 pos to trb
3 data0 neg to add-on
4 data1 neg to trb
>
>
24 LVDS pins data pos to trb
12 LVDS pins GND - to trb
44 LVDS pins general I/O pos to add-on/to trb
 

Connector B

Changed:
<
<
needed for what?
>
>

Pin Signal Polarity (if LVDS) Direction
2 LVDS pins CLK pos to add-on
2 LVDS pins RST pos to add-on
5 pins (no LVDS) JTAG - to add-on
70+1 LVDS pins general I/O (HTDC bus) pos to add-on/to trb
 

-- IngoFroehlich - 05 Sep 2006
 
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