Difference: TRBProgressReports (1 vs. 87)

Revision 87
Changes from r84 to r87
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"
Line: 59 to 59
 
    • enable_a_add_data_line_controller.vhd (program to switch a_add line between internal entities) done
    • trigger_distributor.vhd (It takes the trigger from the TRB and distribute it to all buses): done .
    • PERL script + VHDL program to write/read TDC configuration data into VIRTEX BLOCK of RAM) started
Changed:
<
<
    • TDCs calibration part (send calibration parameters to TDCs, get calibration data): started
>
>
    • TDCs calibration part (send calibration parameters to TDCs, get calibration data): done for one short MB, started for chain of MBs.
 
    • mdc_etrax_interface.vhd (Marek's entity. With this entity we are able to write MDC Addon registers through ETRAX): done

Line: 82 to 82
 
  • Status:
    • 24 Apr 2007: until now I can fix the motherboar's mode lines and I see two tokens back (from MB to Mdc addon), as expected (DSP code). The next step is: add an entity (load_ROC1_tdc_setup.vhd) to the TLD design to load data into TDCs (channel enable, threshold...). Once this is done, I should be able to get data from TDCs every time I send a token with the entity (tdc_readout.vhd). As first approach this data is sended directly to TRBv2.
Deleted:
<
<
 
    • 25 Jul 2007: I can load configuration parameters into TDCs and I read them back. I can do this (in token mode) using a special configuration of working mode line (load_ROC1_data_mode.vhd). I can read "real data" from TDCs. This data shows TDC number(4 bits), TDC channel (4 bits), HIT number(1 bit) and data(10 bits). I read back data from one single channel than I enabled 2 channels and so on. Today I enabled all channels of one short motherboard and I read back the data: all channels/TDCs are visible.Today I started to write a more smart programm to read back "real data", to collect data into a FIFO and send this data with header/trailer to TRB. I would send information of possible errors (no token back, event too long....) in the header/trailer words. After that I'll do the same for all 10 buses. So I'll have 10 FIFOs, one for each bus: FIFO_0,...,FIFO_9. I'll collect event in a bigger FIFO and I'll send the event to TRB.
Changed:
<
<

    • 04 Mar 2008: I write calibration parameters in to TDCs (CAL1) and I read out the calibration data from 1 short MB.
>
>
    • 04 Mar 2008: I write calibration parameters in to TDCs (CAL1) and I read out the calibration data from 1 short MB. The format of the data is temporary. I cannot get yet "real data" and calibration data at the same time.
    • 11 Mar 2008: I get calibration event and normal event together. I start to change dataword format.
 
  • Plans and milestones for next 3 months (04 Mar 2008)
    • Calibration (3 days). I should be able to get calibration data and "real" data from TDC.
Line: 93 to 92
 
    • Threshold setting (3 weeks): the threshold and all other parameters have to be loaded into Virtex's RAM by ETRAX. At the moment the parameters are hard coded in the VHDL code and they cannot be changed.
    • Common stop (3 days). At the moment I generate the common stop internally into the Virtex (on MDC AddOn). Indeed the common stop has to be generated from external electronics.
The previous 3 steps has to be finish at the end of April.
Added:
>
>
In details: we (Attilio and Joern) agreed (07.03.2008) to have a stable bus readout. For the end of April we should be able to configure one bus (1 short MB, 1 long MB, 2 short MBs, 2 long MBs). I'm not considering the case in which on the same bus there are 3 MB (Dubna plane). The bus must be configured (ROC1 and CAL1) and the parameters have to be reloaded by ETRAX (not hard-coded). The calibration will be done for all TDCs and all channels (no rotating mask).
 

    • Design generalization (3 weeks): Ones we will have a reliable readout system I will generalize the design to all buses.
Revision 84
Changes from r81 to r84
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"
Line: 7 to 7
  TIPS about DAQ, kernel, etc.
manual about DAQ readout scripts
TRBvIIHowTo for trb v2
Added:
>
>
AnaSimMay07
 
  1. Quantum Mechanic very well
  2. prepare boards in Krakow to work done
Line: 46 to 47
 

Attilio

Main tasks are:

Changed:
<
<
  • MDC readout system: implement state machines to write ROC1 and CAL1 (configuration files) into MDC motherbards. Write the TDCs readout code and the transmission protocol to send data to TRBv2.
>
>
  • MDC readout system: implement state machines to write ROC1 and CAL1 (configuration files) into MDC motherboards. Write the TDCs readout code and the transmission protocol to send data to TRBv2.
 

Changed:
<
<
  • TDCs configuration part (ROC1):
>
>
  • TDCs configuration part (ROC1 and CAL1):
 
    • load_ROC1_data_mode.vhd (set the mode lines for the CPLD/TDCs working mode): done
    • load_ROC1_tdc_setup.vhd (it loads configuration parameter to one short MB): done
    • trigger_begrun_state.vhd: done . It is missing the calibration part.
Changed:
<
<
    • trigger_handle_tld.vhd: done
>
>
    • trigger_handle_tld.vhd (it synchronize the previous three entities): done
 
    • mode_line_multiplexer.vhd: done
    • common_stop_generator.vhd (it generates cms and other control signals for internal use between entities): done
    • enable_a_add_data_line_controller.vhd (program to switch a_add line between internal entities) done
Changed:
<
<
    • PERL script + VHDL program to write/read TDC configuration data into VIRTEX BLOCK of RAM) not started
    • TDCs calibration part (send calibration parameters to TDCs, get calibration data. Self-calibration?!:..further step): not started
>
>
    • trigger_distributor.vhd (It takes the trigger from the TRB and distribute it to all buses): done .
    • PERL script + VHDL program to write/read TDC configuration data into VIRTEX BLOCK of RAM) started
    • TDCs calibration part (send calibration parameters to TDCs, get calibration data): started
    • mdc_etrax_interface.vhd (Marek's entity. With this entity we are able to write MDC Addon registers through ETRAX): done

 

  • TDC readout:
    • send_token_to_mb.vhd(program to send token into TDCs on motherboards: done
Changed:
<
<
    • tdc_readout.vhd(simple program to get TDCs data. It sends data to TRB. Any FIFO!I used this only to see TDC data and to decode it): done
>
>
    • tdc_readout_and_trb_interface.vhd (it reads the data from internal FIFO and send it to the TRB): done .
 
    • program to send/receive data from/to TRBv2: simulated and started implementation in hardware
Changed:
<
<
    • PERL script to read back/decode TDC configuration data and to decode "real data". I've been thinking a simpler version of our newdecode.c : not started
    • fifo_bus_0.vhd: simulated and started implementaion in hardware.
    • tdc_readout_and_trb_interface.vhd (get/build datawords from extermal bus, stores in a fifo and sends to TRB, with debug information decoded into the trailers): simulated and started implementation in hardware.
>
>
    • my_decode.pl (PERL script to read and decode TDC data): done
    • fifo_bus_0.vhd: done .
 

  • Preparation-understanding MDC-DAQ for next beam time: done
    • DAQ/FEE tests, FEE exchange, noise test: done
Line: 74 to 77
 

  • Helmholtz Research School lecture
    • IInd semester lecture: done
Changed:
<
<

*Priority: readout one MDC motherboard. To do this I would write the simplest program to get data from motherboards, it's an entity that gets data from TDCs, based on fifo. I want to write the transmission protocol to communicate with TRBv2. Ones we see data I'd start to readout all 10 buses with one short motherboard connected. The last step will be the implementation the calibration mode (CAL1).
>
>
    • Spring lectures weeks : not started
    • Summer semester basic lectures-QFT lectures : not started

 
  • Status:
    • 24 Apr 2007: until now I can fix the motherboar's mode lines and I see two tokens back (from MB to Mdc addon), as expected (DSP code). The next step is: add an entity (load_ROC1_tdc_setup.vhd) to the TLD design to load data into TDCs (channel enable, threshold...). Once this is done, I should be able to get data from TDCs every time I send a token with the entity (tdc_readout.vhd). As first approach this data is sended directly to TRBv2.
Changed:
<
<
    • 25 Jul 2007: I can load configuration parameters into TDCs and I read them back. I can do this (in token mode) using a special configuration of working mode line (load_ROC1_data_mode.vhd).
I can read "real data" from TDCs. This data shows TDC number(4 bits), TDC channel (4 bits), HIT number(1 bit) and data(10 bits). I read back data from one single channel than I enabled 2 channels and so on. Today I enabled all channels of one short motherboard and I read back the data: all channels/TDCs are visible! Today I started to write a more smart programm to read back "real data", to collect data into a FIFO and send this data with header/trailer to TRB. I would send information of possible errors (no token back, event too long....) in the header/trailer words. After that I'll do the same for all 10 buses. So I'll have 10 FIFOs, one for each bus: FIFO_0,...,FIFO_9. I'll collect event in a bigger FIFO and I'll send the event to TRB.
>
>
    • 25 Jul 2007: I can load configuration parameters into TDCs and I read them back. I can do this (in token mode) using a special configuration of working mode line (load_ROC1_data_mode.vhd). I can read "real data" from TDCs. This data shows TDC number(4 bits), TDC channel (4 bits), HIT number(1 bit) and data(10 bits). I read back data from one single channel than I enabled 2 channels and so on. Today I enabled all channels of one short motherboard and I read back the data: all channels/TDCs are visible.Today I started to write a more smart programm to read back "real data", to collect data into a FIFO and send this data with header/trailer to TRB. I would send information of possible errors (no token back, event too long....) in the header/trailer words. After that I'll do the same for all 10 buses. So I'll have 10 FIFOs, one for each bus: FIFO_0,...,FIFO_9. I'll collect event in a bigger FIFO and I'll send the event to TRB.
 
Added:
>
>
    • 04 Mar 2008: I write calibration parameters in to TDCs (CAL1) and I read out the calibration data from 1 short MB.

  • Plans and milestones for next 3 months (04 Mar 2008)
    • Calibration (3 days). I should be able to get calibration data and "real" data from TDC.
    • Change the dataword format (2 weeks), as agreed with my colleagues.
    • Threshold setting (3 weeks): the threshold and all other parameters have to be loaded into Virtex's RAM by ETRAX. At the moment the parameters are hard coded in the VHDL code and they cannot be changed.
    • Common stop (3 days). At the moment I generate the common stop internally into the Virtex (on MDC AddOn). Indeed the common stop has to be generated from external electronics.
The previous 3 steps has to be finish at the end of April.

    • Design generalization (3 weeks): Ones we will have a reliable readout system I will generalize the design to all buses.
    • Error handling (3 weeks): I should take care of errors which will happen when we run the full design (10 buses). For example token not back or possibility to disable one bus if it is corrupted..
    • MDC AddOn: design optimization (to discuss in a later step).
    • MDC End Point: software implementation
 

-- AttilioTarantola - 25 Jul 2007
Revision 81
Changes from r78 to r81
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"
Line: 6 to 6
  TIPS about DAQ, kernel, etc.
manual about DAQ readout scripts
Changed:
<
<
HowTo for trb v2
>
>
TRBvIIHowTo for trb v2
 
  1. Quantum Mechanic very well
  2. prepare boards in Krakow to work done
Line: 49 to 49
 
  • MDC readout system: implement state machines to write ROC1 and CAL1 (configuration files) into MDC motherbards. Write the TDCs readout code and the transmission protocol to send data to TRBv2.

  • TDCs configuration part (ROC1):
Changed:
<
<
    • load_ROC1_data_mode.vhd: done
    • load_ROC1_tdc_setup.vhd: simulated and started implementation in hardware
    • trigger_begrun_state.vhd: simulated and started implementation in hardware
    • trigger_handle_tld.vhd: simulated
    • mode_line_multiplexer.vhd: simulated
    • common_stop_generator.vhd: started
    • enable_a_add_data_line_controller.vhd, program to switch a_add line between internal entity: simulated and started implementation in hardware
>
>
    • load_ROC1_data_mode.vhd (set the mode lines for the CPLD/TDCs working mode): done
    • load_ROC1_tdc_setup.vhd (it loads configuration parameter to one short MB): done
    • trigger_begrun_state.vhd: done . It is missing the calibration part.
    • trigger_handle_tld.vhd: done
    • mode_line_multiplexer.vhd: done
    • common_stop_generator.vhd (it generates cms and other control signals for internal use between entities): done
    • enable_a_add_data_line_controller.vhd (program to switch a_add line between internal entities) done
    • PERL script + VHDL program to write/read TDC configuration data into VIRTEX BLOCK of RAM) not started
    • TDCs calibration part (send calibration parameters to TDCs, get calibration data. Self-calibration?!:..further step): not started
 

  • TDC readout:
Changed:
<
<
    • send_token_to_mb.vhd: program to send token into TDCs on motherboards: simulated and started implementation in hardware
    • tdc_readout.vhd: simple program to get TDCs data: simulated and started implementation in hardware
>
>
    • send_token_to_mb.vhd(program to send token into TDCs on motherboards: done
    • tdc_readout.vhd(simple program to get TDCs data. It sends data to TRB. Any FIFO!I used this only to see TDC data and to decode it): done
 
    • program to send/receive data from/to TRBv2: simulated and started implementation in hardware
Added:
>
>
    • PERL script to read back/decode TDC configuration data and to decode "real data". I've been thinking a simpler version of our newdecode.c : not started
    • fifo_bus_0.vhd: simulated and started implementaion in hardware.
    • tdc_readout_and_trb_interface.vhd (get/build datawords from extermal bus, stores in a fifo and sends to TRB, with debug information decoded into the trailers): simulated and started implementation in hardware.
 

  • Preparation-understanding MDC-DAQ for next beam time: done
    • DAQ/FEE tests, FEE exchange, noise test: done
Line: 68 to 73
 
    • MDC operation with cosmics: done

  • Helmholtz Research School lecture
Changed:
<
<
    • IInd semester lecture: started
>
>
    • IInd semester lecture: done
 

*Priority: readout one MDC motherboard. To do this I would write the simplest program to get data from motherboards, it's an entity that gets data from TDCs, based on fifo.
Changed:
<
<
I want to write the transmission protocol to communicate with TRBv2. Ones we see data I'd start to readout a chain of motherboards and then implement the calibration mode (CAL1). -- AttilioTarantola - 13 Feb 2007
>
>
I want to write the transmission protocol to communicate with TRBv2. Ones we see data I'd start to readout all 10 buses with one short motherboard connected. The last step will be the implementation the calibration mode (CAL1).
 
Deleted:
<
<
*Status: until now I can fix the motherboar's mode lines and I see two tokens back (from MB to Mdc addon), as expected (DSP code). The next step is: add an entity (load_ROC1_tdc_setup.vhd) to the TLD design to load data into TDCs (channel enable, threshold...). Once this is done, I should be able to get data from TDCs every time I send a token with the entity (tdc_readout.vhd). As first approach this data is sended directly to TRBv2.
 
Changed:
<
<
-- AttilioTarantola - 24 Apr 2007
>
>
  • Status:
    • 24 Apr 2007: until now I can fix the motherboar's mode lines and I see two tokens back (from MB to Mdc addon), as expected (DSP code). The next step is: add an entity (load_ROC1_tdc_setup.vhd) to the TLD design to load data into TDCs (channel enable, threshold...). Once this is done, I should be able to get data from TDCs every time I send a token with the entity (tdc_readout.vhd). As first approach this data is sended directly to TRBv2.

    • 25 Jul 2007: I can load configuration parameters into TDCs and I read them back. I can do this (in token mode) using a special configuration of working mode line (load_ROC1_data_mode.vhd).
I can read "real data" from TDCs. This data shows TDC number(4 bits), TDC channel (4 bits), HIT number(1 bit) and data(10 bits). I read back data from one single channel than I enabled 2 channels and so on. Today I enabled all channels of one short motherboard and I read back the data: all channels/TDCs are visible! Today I started to write a more smart programm to read back "real data", to collect data into a FIFO and send this data with header/trailer to TRB. I would send information of possible errors (no token back, event too long....) in the header/trailer words. After that I'll do the same for all 10 buses. So I'll have 10 FIFOs, one for each bus: FIFO_0,...,FIFO_9. I'll collect event in a bigger FIFO and I'll send the event to TRB.

-- AttilioTarantola - 25 Jul 2007
 
Revision 78
Changes from r75 to r78
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

Radek

Changed:
<
<
TIPS about DAQ, kernel, etc.
>
>
TIPS about DAQ, kernel, etc.
manual about DAQ readout scripts
HowTo for trb v2
 
  1. Quantum Mechanic very well
  2. prepare boards in Krakow to work done
  3. prepare script, which open xterms and log on into trb done
Line: 45 to 49
 
  • MDC readout system: implement state machines to write ROC1 and CAL1 (configuration files) into MDC motherbards. Write the TDCs readout code and the transmission protocol to send data to TRBv2.

  • TDCs configuration part (ROC1):
Changed:
<
<
    • load_ROC1_data_mode.vhd: simulated
    • load_ROC1_tdc_setup.vhd: simulated
    • trigger_begrun_state.vhd: simulated
>
>
    • load_ROC1_data_mode.vhd: done
    • load_ROC1_tdc_setup.vhd: simulated and started implementation in hardware
    • trigger_begrun_state.vhd: simulated and started implementation in hardware
 
    • trigger_handle_tld.vhd: simulated
    • mode_line_multiplexer.vhd: simulated
    • common_stop_generator.vhd: started
Changed:
<
<
    • enable_a_add_data_line_controller.vhd, program to switch a_add line between internal entity: simulated
>
>
    • enable_a_add_data_line_controller.vhd, program to switch a_add line between internal entity: simulated and started implementation in hardware
 

  • TDC readout:
Changed:
<
<
    • send_token_to_mb.vhd: program to send token into TDCs on motherboards: simulated
    • simple program to get TDCs data: started
    • program to send/receive data from TRBv2: not started

  • MDC addon first hardware test: not started

  • Preparation-understanding MDC-DAQ for next beam time: started
    • DAQ/FEE tests, FEE exchange, noise test: started
    • Full system DAQ test: started
    • MDC operation with cosmics: not started
>
>
    • send_token_to_mb.vhd: program to send token into TDCs on motherboards: simulated and started implementation in hardware
    • tdc_readout.vhd: simple program to get TDCs data: simulated and started implementation in hardware
    • program to send/receive data from/to TRBv2: simulated and started implementation in hardware

  • Preparation-understanding MDC-DAQ for next beam time: done
    • DAQ/FEE tests, FEE exchange, noise test: done
    • Full system DAQ test: done
    • MDC operation with cosmics: done

  • Helmholtz Research School lecture
    • IInd semester lecture: started
 

*Priority: readout one MDC motherboard. To do this I would write the simplest program to get data from motherboards, it's an entity that gets data from TDCs, based on fifo. I want to write the transmission protocol to communicate with TRBv2. Ones we see data I'd start to readout a chain of motherboards and then implement the calibration mode (CAL1).
Line: 67 to 72
 

*Priority: readout one MDC motherboard. To do this I would write the simplest program to get data from motherboards, it's an entity that gets data from TDCs, based on fifo. I want to write the transmission protocol to communicate with TRBv2. Ones we see data I'd start to readout a chain of motherboards and then implement the calibration mode (CAL1).
Deleted:
<
<
  -- AttilioTarantola - 13 Feb 2007
Added:
>
>
*Status: until now I can fix the motherboar's mode lines and I see two tokens back (from MB to Mdc addon), as expected (DSP code). The next step is: add an entity (load_ROC1_tdc_setup.vhd) to the TLD design to load data into TDCs (channel enable, threshold...). Once this is done, I should be able to get data from TDCs every time I send a token with the entity (tdc_readout.vhd). As first approach this data is sended directly to TRBv2.

-- AttilioTarantola - 24 Apr 2007
Revision 75
Changes from r72 to r75
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"
Line: 38 to 38
 

* first priority I would set now for you to the standardized control-pograms for the TRB, like trbctrl init trb0 where the settings for trb0 are read from a trb.tcl script, via the param-library and an linked tcl-interpreter. And the same applies for the hwtrb-readout-programm. It is necessary, that it reads for example it's subevent-id from the config-file, as we will have many TRBs, which all need different subevent-id in the datastream.
Changed:
<
<

Marek

Main tasks are:

  • Crosstalk(CrossTalk) and nonlinearity - TDC calibration started ,
  • Implement internal registers to write to from Etrax:
    • Changing delay of trigger, which is sending to TDC, done
    • Enable/disable direct trigger - without or with Hades trigger bus, done
    • Enable/disable bunch reset after every event or between spill done
  • Generate digital trigger to readout of TDCs by the "T" signal on the Trigger bus, don't wait till the whole trigger tag has been transferred
  • VHDL code for 2GBit transceivers 64 bit -> ( <- ) 16bit test:
    • small test done with 16 bit transmition: memory with random data was send thru optical link done
    • link_converter.vhd - 64 - > 16 bit (16 bit -> 64 bit) simulation done
    • link_converter.vhd - 64 - > 16 bit (16 bit -> 64 bit) hardware application done .
  • I2C for the SPFs
    • simulation done
    • hardware tests started
  • New TRB V2 VHDL code started . Entities:
    • SDRAM interface from Xilinx (MIG - memory interface genarator)
    • tdc_interface.vhd started (has been simulated and tested)
    • lvl1_fifo.vhd started (has been simulated and tested)
    • lvl1_lvl2_busy.vhd - started (has been simulated and tested)
    • trigger_logic.vhd - started (has been simulated and tested)
    • etrax_interface.vhd - started (has been simulated and tested)
    • tlk_interface.vhd - started (has been simulated and tested)
    • other entities (SPI, comunication with DSP...),
    • actual situation: it was possible to read TDC ID and programm with setup data but still checking .. ,
      optical transmition seems to be ok:error pin on TLK2501 during transmition is inactivate,
      together with Radek we wrote comunication protocol and it is working
      All VHDL programs were connected, it was possible to download the data from the TDC's -but without ETRAX. Now we are trying make simple DAQ to download the data with ETRAX.
  • Communication protocol between ETRAX-FS and FPGA(NewProtocolEtraxToFPGA) done
  • MU V2:
    • hardware: MU concentrator, 1.5 GBit link - optical link test started
    • software: MU algorithm - same as old MU, but in VME-CPU not started
  • TRB V1 tests of all channels not started
  • TRB network - some cosmetics needed - started
  • Changing htrbbaseupacker.cc (new header) - started - needs verification with hld file with new data format
>
>

MarekPalka

 

Attilio

Main tasks are:

Line: 83 to 49
 
    • load_ROC1_tdc_setup.vhd: simulated
    • trigger_begrun_state.vhd: simulated
    • trigger_handle_tld.vhd: simulated
Added:
>
>
    • mode_line_multiplexer.vhd: simulated
    • common_stop_generator.vhd: started
    • enable_a_add_data_line_controller.vhd, program to switch a_add line between internal entity: simulated
 

  • TDC readout:
Changed:
<
<
    • send_tonken.vhd: program to send token into TDCs on motherboards: started
>
>
    • send_token_to_mb.vhd: program to send token into TDCs on motherboards: simulated
 
    • simple program to get TDCs data: started
    • program to send/receive data from TRBv2: not started

Line: 93 to 62
 

  • Preparation-understanding MDC-DAQ for next beam time: started
    • DAQ/FEE tests, FEE exchange, noise test: started
Changed:
<
<
    • Full system DAQ test: not started
>
>
    • Full system DAQ test: started
 
    • MDC operation with cosmics: not started

*Priority: readout one MDC motherboard. To do this I would write the simplest program to get data from motherboards, it's an entity that gets data from TDCs, based on fifo.
Revision 72
Changes from r69 to r72
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"
Line: 18 to 18
 
  1. compile the jam program for etrax_fs done HowToDoIt
  2. write a device driver which cooperate with IOP DeviceDriver_IOP,
  3. debugging of crashes and 'enter', It was hardware problem with patches
Added:
>
>
  1. compile jam which uses internal register decrease time of programming FPGA from 3min to 7sec
 
  1. DMA on IOP, started
Changed:
<
<
  1. Readout without DMA, started
>
>
  1. Readout without DMA,
 
  1. communication protocol for TRBv2, done
  2. rwv2 is ready, done
  3. Reading Serial-Number from Tempsens1 and adapting the startupscripts of the Etrax-FS environment to set the MAC-address corresponding a table
Changed:
<
<
Serial Number -> MAC-Address,
>
>
Serial Number -> MAC-Address, started
 
  1. compile the jam, which uses coprocessor,
  2. hwtrb version, which remove TDCheader & TDCtrailer(some kind of compression)
  3. make jam programming faster,
Line: 54 to 55
 
    • hardware tests started
  • New TRB V2 VHDL code started . Entities:
    • SDRAM interface from Xilinx (MIG - memory interface genarator)
Changed:
<
<
    • tdc_interface.vhd started (has been simulated)
    • lvl1_fifo.vhd started (has been simulated)
    • lvl1_lvl2_busy.vhd - started (has been simulated)
    • trigger_logic.vhd - started (has been simulated)
    • etrax_interface.vhd - started (has been simulated)
    • tlk_interface.vhd - started (has been simulated)
>
>
    • tdc_interface.vhd started (has been simulated and tested)
    • lvl1_fifo.vhd started (has been simulated and tested)
    • lvl1_lvl2_busy.vhd - started (has been simulated and tested)
    • trigger_logic.vhd - started (has been simulated and tested)
    • etrax_interface.vhd - started (has been simulated and tested)
    • tlk_interface.vhd - started (has been simulated and tested)
 
    • other entities (SPI, comunication with DSP...),
    • actual situation: it was possible to read TDC ID and programm with setup data but still checking .. ,
      optical transmition seems to be ok:error pin on TLK2501 during transmition is inactivate,
      together with Radek we wrote comunication protocol and it is working
Changed:
<
<
All VHDL programs were connected, in next week most probably it will be possible to download the data from the TDCs'.
>
>
All VHDL programs were connected, it was possible to download the data from the TDC's -but without ETRAX. Now we are trying make simple DAQ to download the data with ETRAX.
 
Deleted:
<
<
  • ETRAX-FS Coprocessor Assembler programming started
 
  • MU V2:
    • hardware: MU concentrator, 1.5 GBit link - optical link test started
    • software: MU algorithm - same as old MU, but in VME-CPU not started
Line: 82 to 82
 
    • load_ROC1_data_mode.vhd: simulated
    • load_ROC1_tdc_setup.vhd: simulated
    • trigger_begrun_state.vhd: simulated
Added:
>
>
    • trigger_handle_tld.vhd: simulated
 

  • TDC readout:
    • send_tonken.vhd: program to send token into TDCs on motherboards: started
Revision 69
Changes from r66 to r69
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"
Line: 18 to 18
 
  1. compile the jam program for etrax_fs done HowToDoIt
  2. write a device driver which cooperate with IOP DeviceDriver_IOP,
  3. debugging of crashes and 'enter', It was hardware problem with patches
Deleted:
<
<
  1. compile images with uClib library, started
 
  1. DMA on IOP, started
  2. Readout without DMA, started
  3. communication protocol for TRBv2, done
Line: 73 to 72
 
    • software: MU algorithm - same as old MU, but in VME-CPU not started
  • TRB V1 tests of all channels not started
  • TRB network - some cosmetics needed - started
Changed:
<
<
  • Changing htrbbaseupacker.cc (new header) - started
>
>
  • Changing htrbbaseupacker.cc (new header) - started - needs verification with hld file with new data format
 

Attilio

Main tasks are:

  • MDC readout system: implement state machines to write ROC1 and CAL1 (configuration files) into MDC motherbards. Write the TDCs readout code and the transmission protocol to send data to TRBv2.
Changed:
<
<
    • load_ROC1_data_mode.vhd: started (has been simulated)
    • load_ROC1_tdc_setup.vhd: started (has been simulated)
    • trigger_begrun_state.vhd: started (has been simulated)
    • program to set token into TDCs on motherboards: not started
    • simple program to get TDCs data: not started
    • programm to send/receive data from TRBv2: not started
    • MDC addon first test..
>
>

  • TDCs configuration part (ROC1):
    • load_ROC1_data_mode.vhd: simulated
    • load_ROC1_tdc_setup.vhd: simulated
    • trigger_begrun_state.vhd: simulated

  • TDC readout:
    • send_tonken.vhd: program to send token into TDCs on motherboards: started
    • simple program to get TDCs data: started
    • program to send/receive data from TRBv2: not started

  • MDC addon first hardware test: not started
 

  • Preparation-understanding MDC-DAQ for next beam time: started
    • DAQ/FEE tests, FEE exchange, noise test: started
Revision 66
Changes from r63 to r66
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"
Line: 17 to 17
 
  1. loading the kernel into the dev-board, done
  2. compile the jam program for etrax_fs done HowToDoIt
  3. write a device driver which cooperate with IOP DeviceDriver_IOP,
Changed:
<
<
  1. debugging of crashes and 'enter', started
>
>
  1. debugging of crashes and 'enter', It was hardware problem with patches
 
  1. compile images with uClib library, started
  2. DMA on IOP, started
  3. Readout without DMA, started
Line: 40 to 40
 

Marek

Main tasks are:

Deleted:
<
<
  • Clean VHDL code trbv1,
  • Trigger code, trigger Tag should be in header : be [trigg tag] [trigg code] [nr of words],
 
  • Crosstalk(CrossTalk) and nonlinearity - TDC calibration started ,
  • Implement internal registers to write to from Etrax:
    • Changing delay of trigger, which is sending to TDC, done
Line: 59 to 57
 
    • SDRAM interface from Xilinx (MIG - memory interface genarator)
    • tdc_interface.vhd started (has been simulated)
    • lvl1_fifo.vhd started (has been simulated)
Changed:
<
<
    • lvl1_lvl2_busy.vhd - started
    • trigger_logic.vhd - started
    • etrax_interface.vhd - started
    • tlk_interface.vhd - started
>
>
    • lvl1_lvl2_busy.vhd - started (has been simulated)
    • trigger_logic.vhd - started (has been simulated)
    • etrax_interface.vhd - started (has been simulated)
    • tlk_interface.vhd - started (has been simulated)
 
    • other entities (SPI, comunication with DSP...),
Changed:
<
<
    • actual situation: it was not possible to read TDC ID,debugging.. ,
      optical transmition seems to be ok:error pin on TLK2501 during transmition is inactivate,
      together with Radek we wrote comunication protocol and it is working(but only on one board!)
>
>
    • actual situation: it was possible to read TDC ID and programm with setup data but still checking .. ,
      optical transmition seems to be ok:error pin on TLK2501 during transmition is inactivate,
      together with Radek we wrote comunication protocol and it is working
      All VHDL programs were connected, in next week most probably it will be possible to download the data from the TDCs'.
 
  • Communication protocol between ETRAX-FS and FPGA(NewProtocolEtraxToFPGA) done
  • ETRAX-FS Coprocessor Assembler programming started
  • MU V2:
Line: 75 to 75
 
  • TRB network - some cosmetics needed - started
  • Changing htrbbaseupacker.cc (new header) - started
Added:
>
>

Attilio

Main tasks are:

  • MDC readout system: implement state machines to write ROC1 and CAL1 (configuration files) into MDC motherbards. Write the TDCs readout code and the transmission protocol to send data to TRBv2.
    • load_ROC1_data_mode.vhd: started (has been simulated)
    • load_ROC1_tdc_setup.vhd: started (has been simulated)
    • trigger_begrun_state.vhd: started (has been simulated)
    • program to set token into TDCs on motherboards: not started
    • simple program to get TDCs data: not started
    • programm to send/receive data from TRBv2: not started
    • MDC addon first test..

  • Preparation-understanding MDC-DAQ for next beam time: started
    • DAQ/FEE tests, FEE exchange, noise test: started
    • Full system DAQ test: not started
    • MDC operation with cosmics: not started
 
Changed:
<
<
- 05 Aug 2005
>
>
*Priority: readout one MDC motherboard. To do this I would write the simplest program to get data from motherboards, it's an entity that gets data from TDCs, based on fifo. I want to write the transmission protocol to communicate with TRBv2. Ones we see data I'd start to readout a chain of motherboards and then implement the calibration mode (CAL1).

-- AttilioTarantola - 13 Feb 2007
 
Revision 63
Changes from r60 to r63
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"
Changed:
<
<

Radek

>
>
 
Added:
>
>

Radek

TIPS about DAQ, kernel, etc.
 
  1. Quantum Mechanic very well
  2. prepare boards in Krakow to work done
  3. prepare script, which open xterms and log on into trb done
Line: 59 to 61
 
    • lvl1_fifo.vhd started (has been simulated)
    • lvl1_lvl2_busy.vhd - started
    • trigger_logic.vhd - started
Changed:
<
<
    • other entities (SPI, comunication with etrax-send registers values from FPGA to etrax, comunication with DSP...),
  • Communication protocol between ETRAX-FS and FPGA(NewProtocolEtraxToFPGA) first ideas
>
>
    • etrax_interface.vhd - started
    • tlk_interface.vhd - started
    • other entities (SPI, comunication with DSP...),
    • actual situation: it was not possible to read TDC ID,debugging.. ,
      optical transmition seems to be ok:error pin on TLK2501 during transmition is inactivate,
      together with Radek we wrote comunication protocol and it is working(but only on one board!)
  • Communication protocol between ETRAX-FS and FPGA(NewProtocolEtraxToFPGA) done
 
  • ETRAX-FS Coprocessor Assembler programming started
  • MU V2:
    • hardware: MU concentrator, 1.5 GBit link - optical link test started
Revision 60
Changes from r57 to r60
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

Radek

Changed:
<
<
Current task: device driver
>
>
 
  1. Quantum Mechanic very well
  2. prepare boards in Krakow to work done
  3. prepare script, which open xterms and log on into trb done
Line: 16 to 16
 
  1. compile the jam program for etrax_fs done HowToDoIt
  2. write a device driver which cooperate with IOP DeviceDriver_IOP,
  3. debugging of crashes and 'enter', started
Added:
>
>
  1. compile images with uClib library, started
 
  1. DMA on IOP, started
  2. Readout without DMA, started
Changed:
<
<
  1. communication protocol for TRBv2, started
>
>
  1. communication protocol for TRBv2, done
  2. rwv2 is ready, done
 
  1. Reading Serial-Number from Tempsens1 and adapting the startupscripts of the Etrax-FS environment to set the MAC-address corresponding a table Serial Number -> MAC-Address,
Revision 57
Changes from r54 to r57
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

Radek

Current task: device driver
Line: 14 to 14
 
  1. prepare environment for axis FS - onlyRAM version, done see: Second version od dev_system -> only RAM
  2. loading the kernel into the dev-board, done
  3. compile the jam program for etrax_fs done HowToDoIt
Changed:
<
<
  1. write a device driver which cooperate with IOP DeviceDriver_IOP
>
>
  1. write a device driver which cooperate with IOP DeviceDriver_IOP,
  2. debugging of crashes and 'enter', started
  3. DMA on IOP, started
  4. Readout without DMA, started
  5. communication protocol for TRBv2, started
 
  1. Reading Serial-Number from Tempsens1 and adapting the startupscripts of the Etrax-FS environment to set the MAC-address corresponding a table Serial Number -> MAC-Address,
  2. compile the jam, which uses coprocessor,
  3. hwtrb version, which remove TDCheader & TDCtrailer(some kind of compression)
Changed:
<
<
  1. make jam programming faster, (1 day)
>
>
  1. make jam programming faster,
 
  1. use standard HADES-parameter scheme (tcl variables), easiest way would be to use the allParam-library and
Changed:
<
<
use external perl-scripts for generating the jam-files (5 days)
  1. prepare script, which put parameters, such as search window to trb (3 days)
>
>
use external perl-scripts for generating the jam-files
  1. prepare script, which put parameters, such as search window to trb
 
  1. perl compilation
  2. workshop for students,
Line: 34 to 38
 

Main tasks are:

  • Clean VHDL code trbv1,
  • Trigger code, trigger Tag should be in header : be [trigg tag] [trigg code] [nr of words],
Changed:
<
<
  • Crosstalk(CrossTalk) and nonlinearity - TDC calibration,
>
>
  • Crosstalk(CrossTalk) and nonlinearity - TDC calibration started ,
 
  • Implement internal registers to write to from Etrax:
    • Changing delay of trigger, which is sending to TDC, done
    • Enable/disable direct trigger - without or with Hades trigger bus, done
Line: 60 to 64
 
    • hardware: MU concentrator, 1.5 GBit link - optical link test started
    • software: MU algorithm - same as old MU, but in VME-CPU not started
  • TRB V1 tests of all channels not started
Changed:
<
<
  • TRB network
>
>
  • TRB network - some cosmetics needed - started
  • Changing htrbbaseupacker.cc (new header) - started
 

- 05 Aug 2005
Revision 54
Changes from r51 to r54
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

Radek

Current task: device driver
Line: 34 to 34
 

Main tasks are:

  • Clean VHDL code trbv1,
  • Trigger code, trigger Tag should be in header : be [trigg tag] [trigg code] [nr of words],
Changed:
<
<
  • Crosstalk and nonlinearity - TDC calibration,
>
>
  • Crosstalk(CrossTalk) and nonlinearity - TDC calibration,
 
  • Implement internal registers to write to from Etrax:
    • Changing delay of trigger, which is sending to TDC, done
    • Enable/disable direct trigger - without or with Hades trigger bus, done
Line: 47 to 47
 
  • I2C for the SPFs
    • simulation done
    • hardware tests started
Changed:
<
<
>
>
  • New TRB V2 VHDL code started . Entities:
 
    • SDRAM interface from Xilinx (MIG - memory interface genarator)
Changed:
<
<
    • tdc_interface.vhd started
    • lvl1_fifo.vhd started
>
>
    • tdc_interface.vhd started (has been simulated)
    • lvl1_fifo.vhd started (has been simulated)
 
    • lvl1_lvl2_busy.vhd - started
Added:
>
>
    • trigger_logic.vhd - started
 
    • other entities (SPI, comunication with etrax-send registers values from FPGA to etrax, comunication with DSP...),
  • Communication protocol between ETRAX-FS and FPGA(NewProtocolEtraxToFPGA) first ideas
Changed:
<
<
  • ETRAX-FS Coprocessor Assembler programming
>
>
  • ETRAX-FS Coprocessor Assembler programming started
 
  • MU V2:
    • hardware: MU concentrator, 1.5 GBit link - optical link test started
    • software: MU algorithm - same as old MU, but in VME-CPU not started
Revision 51
Changes from r48 to r51
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

Radek

Current task: device driver
Line: 36 to 36
 
  • Trigger code, trigger Tag should be in header : be [trigg tag] [trigg code] [nr of words],
  • Crosstalk and nonlinearity - TDC calibration,
  • Implement internal registers to write to from Etrax:
Changed:
<
<
    • Changing delay of trigger, which is sending to TDC,
      (done)
    • Enable/disable direct trigger - without or with Hades trigger bus,
      (done)
    • Enable/disable bunch reset after every event or between spills.
>
>
    • Changing delay of trigger, which is sending to TDC, done
    • Enable/disable direct trigger - without or with Hades trigger bus, done
    • Enable/disable bunch reset after every event or between spill done
 
  • Generate digital trigger to readout of TDCs by the "T" signal on the Trigger bus, don't wait till the whole trigger tag has been transferred
  • VHDL code for 2GBit transceivers 64 bit -> ( <- ) 16bit test:
Changed:
<
<
    • small test done with 16 bit transmition: memory with random data was send thru optical link(success)
    • link_converter.vhd - 64 - > 16 bit (16 bit -> 64 bit) simulation (done)
    • link_converter.vhd - 64 - > 16 bit (16 bit -> 64 bit) hardware application is now during tests(also sendig random data thru optical link),
>
>
    • small test done with 16 bit transmition: memory with random data was send thru optical link done
    • link_converter.vhd - 64 - > 16 bit (16 bit -> 64 bit) simulation done
    • link_converter.vhd - 64 - > 16 bit (16 bit -> 64 bit) hardware application done .
 
  • I2C for the SPFs
Changed:
<
<
    • simulation(done)
    • hardware tests (started)
  • New TRB V2 VHDL code
  • Communication protocol between ETRAX-FS and FPGA
>
>
    • simulation done
    • hardware tests started
  • New TRB V2 VHDL code started entities(TRBv2VHDLCode):
    • SDRAM interface from Xilinx (MIG - memory interface genarator)
    • tdc_interface.vhd started
    • lvl1_fifo.vhd started
    • lvl1_lvl2_busy.vhd - started
    • other entities (SPI, comunication with etrax-send registers values from FPGA to etrax, comunication with DSP...),
  • Communication protocol between ETRAX-FS and FPGA(NewProtocolEtraxToFPGA) first ideas
 
  • ETRAX-FS Coprocessor Assembler programming
  • MU V2:
Changed:
<
<
    • hardware: MU concentrator, 1.5 GBit link (opticla link test started)
    • software: MU algorithm (same as old MU, but in VME-CPU)(not started)
  • TRB V1 tests of all channels
>
>
    • hardware: MU concentrator, 1.5 GBit link - optical link test started
    • software: MU algorithm - same as old MU, but in VME-CPU not started
  • TRB V1 tests of all channels not started
 
  • TRB network
Revision 48
Changes from r45 to r48
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

Radek

Changed:
<
<
Current task: compiling jam & coprocesor
>
>
Current task: device driver
 
  1. Quantum Mechanic very well
  2. prepare boards in Krakow to work done
  3. prepare script, which open xterms and log on into trb done
Line: 14 to 14
 
  1. prepare environment for axis FS - onlyRAM version, done see: Second version od dev_system -> only RAM
  2. loading the kernel into the dev-board, done
  3. compile the jam program for etrax_fs done HowToDoIt
Added:
>
>
  1. write a device driver which cooperate with IOP DeviceDriver_IOP
  2. Reading Serial-Number from Tempsens1 and adapting the startupscripts of the Etrax-FS environment to set the MAC-address corresponding a table Serial Number -> MAC-Address,
 
  1. compile the jam, which uses coprocessor,
  2. hwtrb version, which remove TDCheader & TDCtrailer(some kind of compression)
  3. make jam programming faster, (1 day)
Line: 28 to 32
 

Marek

Main tasks are:

Changed:
<
<
  • Clean VHDL code,
>
>
  • Clean VHDL code trbv1,
 
  • Trigger code, trigger Tag should be in header : be [trigg tag] [trigg code] [nr of words],
Deleted:
<
<
  • Checking Tag with my internal counter and with number in word from TDC,
 
  • Crosstalk and nonlinearity - TDC calibration,
  • Implement internal registers to write to from Etrax:
Changed:
<
<
    • Changing delay of trigger, which is sending to TDC,
    • Enable/disable direct trigger - without or with Hades trigger bus,
>
>
    • Changing delay of trigger, which is sending to TDC,
      (done)
    • Enable/disable direct trigger - without or with Hades trigger bus,
      (done)
 
    • Enable/disable bunch reset after every event or between spills.
Changed:
<
<
  • Generate digital trigger to readout of TDCs by the "T" signal on the Trigger bus, don't wait till the whole trigger tag has been transferred
>
>
  • Generate digital trigger to readout of TDCs by the "T" signal on the Trigger bus, don't wait till the whole trigger tag has been transferred
  • VHDL code for 2GBit transceivers 64 bit -> ( <- ) 16bit test:
    • small test done with 16 bit transmition: memory with random data was send thru optical link(success)
    • link_converter.vhd - 64 - > 16 bit (16 bit -> 64 bit) simulation (done)
    • link_converter.vhd - 64 - > 16 bit (16 bit -> 64 bit) hardware application is now during tests(also sendig random data thru optical link),
  • I2C for the SPFs
    • simulation(done)
    • hardware tests (started)
  • New TRB V2 VHDL code
  • Communication protocol between ETRAX-FS and FPGA
  • ETRAX-FS Coprocessor Assembler programming
  • MU V2:
    • hardware: MU concentrator, 1.5 GBit link (opticla link test started)
    • software: MU algorithm (same as old MU, but in VME-CPU)(not started)
  • TRB V1 tests of all channels
  • TRB network
 

- 05 Aug 2005
Revision 45
Changes from r42 to r45
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

Radek

Current task: compiling jam & coprocesor
Line: 10 to 10
 
  1. compile EPICS on trb done EtraxEPICSHowTo
  2. EPICS -> prepare some testings application done radek@depc187:/home/radek/devboard-work_2.4/apps/epics/base-3.14.8.2/src/makeBaseApp/bin/linux-cris I still have no idea, how can I use casexample & caMonitor
  3. prepare environment for Coimbra, done
Changed:
<
<
  1. prepare environment for axis FS, done not tested Tips
>
>
  1. prepare environment for axis FS, done Tips
  2. prepare environment for axis FS - onlyRAM version, done see: Second version od dev_system -> only RAM
 
  1. loading the kernel into the dev-board, done
Changed:
<
<
  1. compile the jam program for etrax_fs done
>
>
  1. compile the jam program for etrax_fs done HowToDoIt
 
  1. compile the jam, which uses coprocessor,
  2. hwtrb version, which remove TDCheader & TDCtrailer(some kind of compression)
  3. make jam programming faster, (1 day)
Revision 42
Changes from r39 to r42
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

Radek

Changed:
<
<
Current task: loading the kernel
>
>
Current task: compiling jam & coprocesor
 
  1. Quantum Mechanic very well
  2. prepare boards in Krakow to work done
  3. prepare script, which open xterms and log on into trb done
Line: 11 to 11
 
  1. EPICS -> prepare some testings application done radek@depc187:/home/radek/devboard-work_2.4/apps/epics/base-3.14.8.2/src/makeBaseApp/bin/linux-cris I still have no idea, how can I use casexample & caMonitor
  2. prepare environment for Coimbra, done
  3. prepare environment for axis FS, done not tested Tips
Changed:
<
<
  1. loading the kernel into the dev-board, auto-negotiation mechanism between Ethernet interfaces on dev-board and server
>
>
  1. loading the kernel into the dev-board, done
  2. compile the jam program for etrax_fs done
  3. compile the jam, which uses coprocessor,
 
  1. hwtrb version, which remove TDCheader & TDCtrailer(some kind of compression)
  2. make jam programming faster, (1 day)
  3. use standard HADES-parameter scheme (tcl variables), easiest way would be to use the allParam-library and
Revision 39
Changes from r36 to r39
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

Radek

Changed:
<
<
Current task: soy como Linux admin
>
>
Current task: loading the kernel
 
  1. Quantum Mechanic very well
  2. prepare boards in Krakow to work done
  3. prepare script, which open xterms and log on into trb done
  4. simple unpacker for trb in Cracow done
  5. prepare 'init daq' applications done radek@depc187:/home/radek/devboard-work_2.4/DAQ
Changed:
<
<
  1. compile EPICS on trb done HowTo
>
>
  1. compile EPICS on trb done EtraxEPICSHowTo
 
  1. EPICS -> prepare some testings application done radek@depc187:/home/radek/devboard-work_2.4/apps/epics/base-3.14.8.2/src/makeBaseApp/bin/linux-cris I still have no idea, how can I use casexample & caMonitor
  2. prepare environment for Coimbra, done
  3. prepare environment for axis FS, done not tested Tips
Changed:
<
<
  1. prepare perl script to put Shower parameters to Oracle DB, (1 day)
>
>
  1. loading the kernel into the dev-board, auto-negotiation mechanism between Ethernet interfaces on dev-board and server
 
  1. hwtrb version, which remove TDCheader & TDCtrailer(some kind of compression)
  2. make jam programming faster, (1 day)
  3. use standard HADES-parameter scheme (tcl variables), easiest way would be to use the allParam-library and
Revision 36
Changes from r33 to r36
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

Radek

Current task: soy como Linux admin
Line: 10 to 10
 
  1. compile EPICS on trb done HowTo
  2. EPICS -> prepare some testings application done radek@depc187:/home/radek/devboard-work_2.4/apps/epics/base-3.14.8.2/src/makeBaseApp/bin/linux-cris I still have no idea, how can I use casexample & caMonitor
  3. prepare environment for Coimbra, done
Added:
>
>
  1. prepare environment for axis FS, done not tested Tips
 
  1. prepare perl script to put Shower parameters to Oracle DB, (1 day)
Deleted:
<
<
  1. prepare environment for axis FS, (1 day)
 
  1. hwtrb version, which remove TDCheader & TDCtrailer(some kind of compression)
  2. make jam programming faster, (1 day)
  3. use standard HADES-parameter scheme (tcl variables), easiest way would be to use the allParam-library and
Revision 33
Changes from r30 to r33
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

Radek

Current task: soy como Linux admin
Line: 9 to 9
 
  1. prepare 'init daq' applications done radek@depc187:/home/radek/devboard-work_2.4/DAQ
  2. compile EPICS on trb done HowTo
  3. EPICS -> prepare some testings application done radek@depc187:/home/radek/devboard-work_2.4/apps/epics/base-3.14.8.2/src/makeBaseApp/bin/linux-cris I still have no idea, how can I use casexample & caMonitor
Added:
>
>
  1. prepare environment for Coimbra, done
 
  1. prepare perl script to put Shower parameters to Oracle DB, (1 day)
Changed:
<
<
  1. prepare environment for Coimbra, (1 day)
>
>
  1. prepare environment for axis FS, (1 day)
 
  1. hwtrb version, which remove TDCheader & TDCtrailer(some kind of compression)
  2. make jam programming faster, (1 day)
  3. use standard HADES-parameter scheme (tcl variables), easiest way would be to use the allParam-library and use external perl-scripts for generating the jam-files (5 days)
  4. prepare script, which put parameters, such as search window to trb (3 days)
  5. perl compilation
Added:
>
>
  1. workshop for students,
 

* first priority I would set now for you to the standardized control-pograms for the TRB, like trbctrl init trb0 where the settings for trb0 are read from a trb.tcl script, via the param-library and an linked tcl-interpreter. And the same applies for the hwtrb-readout-programm. It is necessary, that it reads for example it's subevent-id from the config-file, as we will have many TRBs, which all need different subevent-id in the datastream.
Revision 30
Changes from r27 to r30
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

Radek

Changed:
<
<
Current task: init scripts
>
>
Current task: soy como Linux admin
 
  1. Quantum Mechanic very well
  2. prepare boards in Krakow to work done
  3. prepare script, which open xterms and log on into trb done
  4. simple unpacker for trb in Cracow done
Deleted:
<
<
  1. hwtrb version, which remove TDCheader & TDCtrailer(some kind of compression)
 
  1. prepare 'init daq' applications done radek@depc187:/home/radek/devboard-work_2.4/DAQ
  2. compile EPICS on trb done HowTo
Changed:
<
<
  1. EPICS -> prepare some testings application, (4 day)
>
>
  1. EPICS -> prepare some testings application done radek@depc187:/home/radek/devboard-work_2.4/apps/epics/base-3.14.8.2/src/makeBaseApp/bin/linux-cris I still have no idea, how can I use casexample & caMonitor
 
  1. prepare perl script to put Shower parameters to Oracle DB, (1 day)
Added:
>
>
  1. prepare environment for Coimbra, (1 day)
  2. hwtrb version, which remove TDCheader & TDCtrailer(some kind of compression)
 
  1. make jam programming faster, (1 day)
  2. use standard HADES-parameter scheme (tcl variables), easiest way would be to use the allParam-library and use external perl-scripts for generating the jam-files (5 days)
Revision 27
Changes from r24 to r27
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

Radek

Changed:
<
<
Current task: epics-manual
>
>
Current task: init scripts
 
  1. Quantum Mechanic very well
  2. prepare boards in Krakow to work done
Deleted:
<
<
  1. make jam programming faster, (1 day)
 
  1. prepare script, which open xterms and log on into trb done
Added:
>
>
  1. simple unpacker for trb in Cracow done
  2. hwtrb version, which remove TDCheader & TDCtrailer(some kind of compression)
  3. prepare 'init daq' applications done radek@depc187:/home/radek/devboard-work_2.4/DAQ
 
  1. compile EPICS on trb done HowTo
Added:
>
>
  1. EPICS -> prepare some testings application, (4 day)
  2. prepare perl script to put Shower parameters to Oracle DB, (1 day)
  3. make jam programming faster, (1 day)
 
  1. use standard HADES-parameter scheme (tcl variables), easiest way would be to use the allParam-library and use external perl-scripts for generating the jam-files (5 days)
  2. prepare script, which put parameters, such as search window to trb (3 days)
  3. perl compilation
Deleted:
<
<
  1. simple unpacker for trb in Cracow done
  2. hwtrb version, which remove TDCheader & TDCtrailer(some kind of compression)
 

* first priority I would set now for you to the standardized control-pograms for the TRB, like trbctrl init trb0 where the settings for trb0 are read from a trb.tcl script, via the param-library and an linked tcl-interpreter. And the same applies for the hwtrb-readout-programm. It is necessary, that it reads for example it's subevent-id from the config-file, as we will have many TRBs, which all need different subevent-id in the datastream.
Revision 24
Changes from r21 to r24
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

Radek

Changed:
<
<
Current task: epics
>
>
Current task: epics-manual
 
  1. Quantum Mechanic very well
  2. prepare boards in Krakow to work done
  3. make jam programming faster, (1 day)
  4. prepare script, which open xterms and log on into trb done
Changed:
<
<
  1. compile EPICS on trb (3 days)
>
>
  1. compile EPICS on trb done HowTo
 
  1. use standard HADES-parameter scheme (tcl variables), easiest way would be to use the allParam-library and use external perl-scripts for generating the jam-files (5 days)
  2. prepare script, which put parameters, such as search window to trb (3 days)
  3. perl compilation
  4. simple unpacker for trb in Cracow done
  5. hwtrb version, which remove TDCheader & TDCtrailer(some kind of compression)
Deleted:
<
<

EPICS status

in progress...
Below steps are needed (for now)
   . init_env
   cd ~/devboard-work_2.4/apps/epics/base-3.14.8.2
   vim ./configure/CONFIG.gnuCommon
   RANLIB = /home/radek/cris/ranlib-cris
   vim configure/os/CONFIG.Common.linux-cris
   ARCH_DEP_CPPFLAGS += -D_cris_ -I /home/radek/cris/cris-axis-linux-gnu/sys-include
   vim src/libCom/env/bldEnvData.pl:
   $env_dir    = abs_path("./env");
   gmake EPICS_HOST_ARCH="linux-x86" T_A="linux-cris"
   cp  ../copy/src/as/asLib.h src/as/ ; cp ../copy/src/db/dbAccessDefs.h src/db/;cp ../copy/src/dbStatic/*.h src/dbStatic/;cp ../copy/src/gdd/*.h src/gdd/
   cd src/libCom
   add 'r' after ar-cris in the comman line
   cd -
 

* first priority I would set now for you to the standardized control-pograms for the TRB, like trbctrl init trb0 where the settings for trb0 are read from a trb.tcl script, via the param-library and an linked tcl-interpreter. And the same applies for the hwtrb-readout-programm. It is necessary, that it reads for example it's subevent-id from the config-file, as we will have many TRBs, which all need different subevent-id in the datastream.
Revision 21
Changes from r18 to r21
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

Radek

Changed:
<
<
Current task: Quantum Mechanic till 9 may
>
>
Current task: epics
  1. Quantum Mechanic very well
 
  1. prepare boards in Krakow to work done
  2. make jam programming faster, (1 day)
  3. prepare script, which open xterms and log on into trb done
Line: 10 to 11
  use external perl-scripts for generating the jam-files (5 days)
  1. prepare script, which put parameters, such as search window to trb (3 days)
  2. perl compilation
Changed:
<
<
  1. simple unpacker for trb in Cracow done
>
>
  1. simple unpacker for trb in Cracow done
 
  1. hwtrb version, which remove TDCheader & TDCtrailer(some kind of compression)
Added:
>
>

EPICS status

in progress...
Below steps are needed (for now)
   . init_env
   cd ~/devboard-work_2.4/apps/epics/base-3.14.8.2
   vim ./configure/CONFIG.gnuCommon
   RANLIB = /home/radek/cris/ranlib-cris
   vim configure/os/CONFIG.Common.linux-cris
   ARCH_DEP_CPPFLAGS += -D_cris_ -I /home/radek/cris/cris-axis-linux-gnu/sys-include
   vim src/libCom/env/bldEnvData.pl:
   $env_dir    = abs_path("./env");
   gmake EPICS_HOST_ARCH="linux-x86" T_A="linux-cris"
   cp  ../copy/src/as/asLib.h src/as/ ; cp ../copy/src/db/dbAccessDefs.h src/db/;cp ../copy/src/dbStatic/*.h src/dbStatic/;cp ../copy/src/gdd/*.h src/gdd/
   cd src/libCom
   add 'r' after ar-cris in the comman line
   cd -
 

* first priority I would set now for you to the standardized control-pograms for the TRB, like trbctrl init trb0 where the settings for trb0 are read from a trb.tcl script, via the param-library and an linked tcl-interpreter. And the same applies for the hwtrb-readout-programm. It is necessary, that it reads for example it's subevent-id from the config-file, as we will have many TRBs, which all need different subevent-id in the datastream.
Revision 18
Changes from r15 to r18
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

Radek

Current task: Quantum Mechanic till 9 may
Line: 9 to 9
 
  1. use standard HADES-parameter scheme (tcl variables), easiest way would be to use the allParam-library and use external perl-scripts for generating the jam-files (5 days)
  2. prepare script, which put parameters, such as search window to trb (3 days)
Added:
>
>
  1. perl compilation
  2. simple unpacker for trb in Cracow done
  3. hwtrb version, which remove TDCheader & TDCtrailer(some kind of compression)
 
Deleted:
<
<
to Michael-> could you sort these tasks according to priorities Michael: done, but these priorities are not fixed. If you have problems with one topic, just continue with the next. If the working times, which I put at the tasks are exceeded, then please let us talk about it. Maybe then we have to change priorities. Remember: We should not aim for 100% solutions. Each task should make an significat improvement on the topic, but no revolution or perfect thing..
  • hwtrb is working now. Data from Etrax are collecting by eventbuilder.
  • keep in mind: 50 IP-numbers for de-etrax001 - de-etrax050 with the following MAC-addresses: 00-40-8c-ad-e5-01 to 00-40-8c-ad-e5-32
  • how to put the different MAC-numbers to the TRB-flash, maybe without having a special full flash for each TRB. And instead of using fixed IP-numbers you could use a dhcp-client to get the IP-number....
 
  • first priority I would set now for you to the standardized control-pograms for the TRB, like trbctrl init trb0 where the settings for trb0 are read from a trb.tcl script, via the param-library and an linked tcl-interpreter. And the same applies for the hwtrb-readout-programm. It is necessary, that it reads for example it's subevent-id from the config-file, as we will have many TRBs, which all need different subevent-id in the datastream.
Deleted:
<
<
To do:
prepare DAQ system in Cracow done 1. task
to introduce 'interrupt-driven operation' and 'DMA', I need to write kernel module instead of 'usual' application. Michael: I think this is not important anymore, as we see that with the large DP-RAM we can live easily with polling no know-how for now last task
prepare some histograms to present the board talk what is needed 3. task
standarization the application I'm thinking about it 2. task
perl compilation I tried if Time==Free
improve the speed of transfer(5x) 1. task, done! It was a syslog statement after each event...

 

Marek

Main tasks are:

Revision 15
Changes from r12 to r15
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

Radek

Added:
>
>
Current task: Quantum Mechanic till 9 may
  1. prepare boards in Krakow to work done
  2. make jam programming faster, (1 day)
  3. prepare script, which open xterms and log on into trb done
  4. compile EPICS on trb (3 days)
  5. use standard HADES-parameter scheme (tcl variables), easiest way would be to use the allParam-library and use external perl-scripts for generating the jam-files (5 days)
  6. prepare script, which put parameters, such as search window to trb (3 days)
 
Added:
>
>
to Michael-> could you sort these tasks according to priorities Michael: done, but these priorities are not fixed. If you have problems with one topic, just continue with the next. If the working times, which I put at the tasks are exceeded, then please let us talk about it. Maybe then we have to change priorities. Remember: We should not aim for 100% solutions. Each task should make an significat improvement on the topic, but no revolution or perfect thing..
 
  • hwtrb is working now. Data from Etrax are collecting by eventbuilder.
  • keep in mind: 50 IP-numbers for de-etrax001 - de-etrax050 with the following MAC-addresses: 00-40-8c-ad-e5-01 to 00-40-8c-ad-e5-32
  • how to put the different MAC-numbers to the TRB-flash, maybe without having a special full flash for each TRB. And instead of using fixed IP-numbers you could use a dhcp-client to get the IP-number....
  • first priority I would set now for you to the standardized control-pograms for the TRB, like trbctrl init trb0 where the settings for trb0 are read from a trb.tcl script, via the param-library and an linked tcl-interpreter. And the same applies for the hwtrb-readout-programm. It is necessary, that it reads for example it's subevent-id from the config-file, as we will have many TRBs, which all need different subevent-id in the datastream.
    To do:
    prepare DAQ system in Cracow done 1. task
Changed:
<
<
to introduce 'interrupt-driven operation' and 'DMA', I need to write kernel module instead of 'usual' application no know-how for now last task
>
>
to introduce 'interrupt-driven operation' and 'DMA', I need to write kernel module instead of 'usual' application. Michael: I think this is not important anymore, as we see that with the large DP-RAM we can live easily with polling no know-how for now last task
 
prepare some histograms to present the board talk what is needed 3. task
standarization the application I'm thinking about it 2. task
perl compilation I tried if Time==Free
Changed:
<
<
improve the speed of transfer(5x) 1. task
>
>
improve the speed of transfer(5x) 1. task, done! It was a syslog statement after each event...
 

Marek

Revision 12
Changes from r9 to r12
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

Radek

Line: 12 to 12
 
prepare some histograms to present the board talk what is needed 3. task
standarization the application I'm thinking about it 2. task
perl compilation I tried if Time==Free
Changed:
<
<

>
>
improve the speed of transfer(5x) 1. task
 

Marek

Changed:
<
<
  • DTU code and RPCboardcontroller code were marged. For now main cases are:
    - Test DTU and "glue code" working together - via signal analyzer,
    - Test RPC code and "glue code" working together - via signal analyzer,
    - Test whole RPC code,
    - Plug DTU device and test with whole board.

>
>

Main tasks are:

  • Clean VHDL code,
  • Trigger code, trigger Tag should be in header : be [trigg tag] [trigg code] [nr of words],
  • Checking Tag with my internal counter and with number in word from TDC,
  • Crosstalk and nonlinearity - TDC calibration,
  • Implement internal registers to write to from Etrax:
    • Changing delay of trigger, which is sending to TDC,
    • Enable/disable direct trigger - without or with Hades trigger bus,
    • Enable/disable bunch reset after every event or between spills.
  • Generate digital trigger to readout of TDCs by the "T" signal on the Trigger bus, don't wait till the whole trigger tag has been transferred
 

- 05 Aug 2005
Revision 9
Changes from r6 to r9
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

Radek

  • hwtrb is working now. Data from Etrax are collecting by eventbuilder.
  • keep in mind: 50 IP-numbers for de-etrax001 - de-etrax050 with the following MAC-addresses: 00-40-8c-ad-e5-01 to 00-40-8c-ad-e5-32
Changed:
<
<
  • how to put the different MAC-numbers to the TRB-flash, maybe without having a special full flash for each TRB. And
instead of using fixed IP-numbers you could use a dhcp-client to get the IP-number....
>
>
  • how to put the different MAC-numbers to the TRB-flash, maybe without having a special full flash for each TRB. And instead of using fixed IP-numbers you could use a dhcp-client to get the IP-number....
  • first priority I would set now for you to the standardized control-pograms for the TRB, like trbctrl init trb0 where the settings for trb0 are read from a trb.tcl script, via the param-library and an linked tcl-interpreter. And the same applies for the hwtrb-readout-programm. It is necessary, that it reads for example it's subevent-id from the config-file, as we will have many TRBs, which all need different subevent-id in the datastream.
  To do:
Changed:
<
<
prepare DAQ system in Cracow 1 week 1. task
to introduce 'interrupt-driven operation' and 'DMA', I need write kernel module instead of 'usual' application no know-how for now last task
>
>
prepare DAQ system in Cracow done 1. task
to introduce 'interrupt-driven operation' and 'DMA', I need to write kernel module instead of 'usual' application no know-how for now last task
 
prepare some histograms to present the board talk what is needed 3. task
standarization the application I'm thinking about it 2. task
perl compilation I tried if Time==Free
Revision 6
Changes from r3 to r6
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"

Radek

Changed:
<
<
  • Segmentation fault on ETRAX -> the problem is in the 'rt' library, one cannot use shm_open(). This system function return -1.
    11:40 -> this means ''not implemented in system'' why?
    12:00 -> ''System V IPC' is NOT enabled in your kernel configuration
    15:30-> compilation of new kernel was done, above point is now enough, I have to add /dev/shm directory and mount it 17:00-> I can't change fstab on depc152, I have done it directly on hades18: memnet is working now, but I have new message: creating shared memory "subevtqueue": Function not implemented.. I have created program shm_foo and the share memory is orking for sure.
    The problem is with the sem_unlink() function ->it's system function too
    after 21:00 smile I have cut out the headers <semaphore.h>(it's system header), and now I'm using compat library.
    now the error is: opening network transport depc152.gsi.de:2222: Invalid argument, I have no idea which argument is ok.
    In friday I want to prepare evtbuider application.
  • main dir: MAIN=/home/radek/new_axis/axis/devboard_82/apps
  • compat source && library: MAIN/compat && MAIN/my_libs
  • hadaq source && library: MAIN/hadaq_lib && && MAIN/my_libs. If one prepare hadaq library then one has to read Makefile in source dir
    FRIDAY
    Problem in evtbuilder -> seg fault in functions *Param, I try see where exactly
    -> desParam() -> see apps/my_allParam/allParam.c Line:332
    next point: we have to run the RPC service first->Run rpc.portmap first, otherwise RPC services are not available
    how can make new kernel:
    cd /home/trebacz/new_axis/axis/devboard_82/os/linux ; make menuconfig ; cd ../.. ; make kernel ; make images ; ./kflash
    *all applications from etrax are in /home/trebacz/new_axis/axis/devboard_82/applicationFromEtraxBeforeNewKernel

Radek, please don't compile the eventbuilder on the ETRAX. The eventbuilder has to run on any linux-box, but not on the ETRAX. But anyhow, it would be nice, if the RPC-is working on the ETRAX, to get the NFS-client running... Michael
>
>
  • hwtrb is working now. Data from Etrax are collecting by eventbuilder.
  • keep in mind: 50 IP-numbers for de-etrax001 - de-etrax050 with the following MAC-addresses: 00-40-8c-ad-e5-01 to 00-40-8c-ad-e5-32
  • how to put the different MAC-numbers to the TRB-flash, maybe without having a special full flash for each TRB. And
instead of using fixed IP-numbers you could use a dhcp-client to get the IP-number....
To do:
prepare DAQ system in Cracow 1 week 1. task
to introduce 'interrupt-driven operation' and 'DMA', I need write kernel module instead of 'usual' application no know-how for now last task
prepare some histograms to present the board talk what is needed 3. task
standarization the application I'm thinking about it 2. task
perl compilation I tried if Time==Free
 

Marek

Revision 3
Changes from r1 to r3
Line: 1 to 1
 
META TOPICPARENT name="TDCReadoutBoard"
Deleted:
<
<
 

Radek

  • Segmentation fault on ETRAX -> the problem is in the 'rt' library, one cannot use shm_open(). This system function return -1.
Line: 25 to 23
  *all applications from etrax are in /home/trebacz/new_axis/axis/devboard_82/applicationFromEtraxBeforeNewKernel

Added:
>
>
Radek, please don't compile the eventbuilder on the ETRAX. The eventbuilder has to run on any linux-box, but not on the ETRAX. But anyhow, it would be nice, if the RPC-is working on the ETRAX, to get the NFS-client running... Michael
 

Marek

Added:
>
>
  • DTU code and RPCboardcontroller code were marged. For now main cases are:
    - Test DTU and "glue code" working together - via signal analyzer,
    - Test RPC code and "glue code" working together - via signal analyzer,
    - Test whole RPC code,
    - Plug DTU device and test with whole board.

 

 
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