Difference: TRBUseDocumentation (1 vs. 2)

Revision 2
14 Jul 2006 - Main.MarekPalka
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META TOPICPARENT name="TDCReadoutBoard"
-- MichaelTraxler - 22 Nov 2005
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  - To enable(1) or disable(0) test signal we have to write from Etrax to FPGA register. This register is at 74 address.
./rw w 74 0|1
Added:
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List of thigs which should be prepared, taken and done before assembling whole TRB system outside the GSI

- Cables for 8930E-080178-MS connector. TDC LVDS signals - four cables,
- Cables for ZF5-20-01 connector (JTL). Two cables and two spare,
- Power supply: 48 V min 0.5 A current ,
- Power supply cable,
- Generator for trigger without HADES bus and for tests,
- diff -> LVDS convertor (build by Michael),
- Cables from generator to JTL connector. From output of generator to JTL connector - 2 signals (test, trigger),
- Ethernet cable,
- Minicom cable,
- Prepere NFS,
- Prepere cernel for etrax,
- Copy everything from GSI etrax NFS .
 
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