Difference: TrbNetRegIO (1 vs. 18)

Revision 18
11 Sep 2009 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetEntities"

Reading and Writing registers over the network

TrbNetRegIO is a simple interface to read and write registers inside your application from anywhere on the network. The width of the registers is fixed to 32 Bit while 16Bit addresses are used.
Line: 103 to 103
 
INIT_ADDRESS 16 Address, the endpoint should have on startup
INIT_UNIQUE_ID 63 The unique id on startup
Changed:
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Other Features

RegIO also serves as a base to several other applications like SPIFlashProgramming.
 

-- JanMichel - 13 Oct 2008
Revision 17
08 Jun 2009 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetEntities"

Reading and Writing registers over the network

TrbNetRegIO is a simple interface to read and write registers inside your application from anywhere on the network. The width of the registers is fixed to 32 Bit while 16Bit addresses are used.
Line: 7 to 7
 
00 1F internally writeable registers common status registers (CommonStatusRegister)
20 3F network writeable registers common ctrl registers (CommonStatusRegister#CommonControlRegister)
40 48 ROM board information ROM
Changed:
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<
50 5F RAM board information RAM (e.g. SubEvtId...)
>
>
50 5F Times board timers
 
60 7F   unused
80 BF internally writeable registers user defined status registers
C0 FF network writeable registers user defined control registers
Revision 16
19 Dec 2008 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetEntities"

Reading and Writing registers over the network

TrbNetRegIO is a simple interface to read and write registers inside your application from anywhere on the network. The width of the registers is fixed to 32 Bit while 16Bit addresses are used.
Line: 66 to 66
  Besides, there's a generic register for setting control signals and reading back; this entity can also used as base for handlers of more complex tasks (like implementing a slow I2C master, as RICH needs it).
Changed:
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Just ask me for source code smile
>
>
Just ask me for source code smile (Also available in the cvs, repository rich_adcm)
 

-- MichaelBoehmer - 16 Dec 2008
Line: 91 to 91
 
DAT_WRITE_ACK_IN 1 write data has been accepted
DAT_NO_MORE_DATA_IN 1 finish transfer / no more data
DAT_UNKNOWN_ADDR_IN 1 unused address
Changed:
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<
DAT_TIMEOUT_OUT 1 endpoint timed out, access is broken
>
>
DAT_TIMEOUT_OUT 1 endpoint timed out, access is canceled
 

Generic Range Description
Line: 101 to 101
 
USED_CTRL_REGS vector width: NUM_CTRL_REGS Which of the addressable register are used
USED_CTRL_BITMASK vector width: 2**NUM_CTRL_REGS*32 which of the bits of the used registers are used
INIT_ADDRESS 16 Address, the endpoint should have on startup
Changed:
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INIT_UNIQUE_ID 96 The unique id on startup
>
>
INIT_UNIQUE_ID 63 The unique id on startup
 

Revision 15
16 Dec 2008 - Main.MichaelBoehmer
Line: 1 to 1
 
META TOPICPARENT name="TrbNetEntities"

Reading and Writing registers over the network

TrbNetRegIO is a simple interface to read and write registers inside your application from anywhere on the network. The width of the registers is fixed to 32 Bit while 16Bit addresses are used.
Line: 59 to 59
 

-- MichaelBoehmer - 15 Dec 2008
Added:
>
>

The SLAVE_BUS - an example for implementation

I have written a small example VHDL code which allows easy implementation of own (also more complex) registers / handlers on the DAT_* bus of TrbNetRegIO. It consists of a "bus handler" which converts the DAT_* signals to simple select, read and write strobes, and handles BUSY and ACK response from the slave entities. TIMEOUT and UNKNOWN_ADDR are also handled correctly. Besides, there's a generic register for setting control signals and reading back; this entity can also used as base for handlers of more complex tasks (like implementing a slow I2C master, as RICH needs it).

Just ask me for source code smile

-- MichaelBoehmer - 16 Dec 2008
 

Ports & Generics

TrbNetRegIO connects to the network with a standard API-interface that is not shown here. The ports towards the application are as follows:
Revision 14
15 Dec 2008 - Main.MichaelBoehmer
Line: 1 to 1
 
META TOPICPARENT name="TrbNetEntities"

Reading and Writing registers over the network

TrbNetRegIO is a simple interface to read and write registers inside your application from anywhere on the network. The width of the registers is fixed to 32 Bit while 16Bit addresses are used.
Line: 45 to 45
 

Access handling

Changed:
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TrbNetRegIO tries to handle all accesses to registers in a way which inhibits the "GTB effect". Accessing a non-existing register or an entitiy on the internal data bus which has deceased may under no circumstances lock up the channel.
>
>
TrbNetRegIO tries to handle all accesses to registers in a way which inhibits the "GTB effect". Accessing a non-existing register or an entitiy on the internal data bus which has deceased may under no circumstances lock up the slow control channel. Therefore the interface to the user register space must be bulletproof and completely decoupled from the slow control endpoint.
 
Changed:
<
<
The following rules are proposed to avoid deadlocks (names of non-existing signals are proposals only and subject to change):
>
>
The TrbNetRegIO entity will handle an automatic timeout for accesses to the DAT_* bus. This timeout is a constant and the same for all TRBnet component. The value suggested here is 32 clock cycles yielding in 320ns, which is slow enough for slow control.
 
Changed:
<
<
  • all accesses on the internal data bus must be acknowledged
  • all accesses must be completed in a short period of time (128 100MHz clock cycles)
  • TrbNetRegIO implements a timeout counter for accesses to the internal data bus
  • user entities acknowledge valid register accesses with data transfer by DAT_DATAREADY_IN on reads and DAT_WRITEACK_IN on writes
  • in case of FIFOs (et al) where the register exists but has no data to send (read) or may not accept data (write) user entities use DAT_NO_MORE_DATA_IN (this gets translated to a short packet TRM in the endpoint)
  • in case of not existing registers user entities acknowledge by DAT_NOT_EXISTS_IN (this gets translated to a short packet TRM in the endpoint)
  • in case of DAT_NO_MORE_DATA_IN and DAT_NOT_EXISTS_IN error bits in the TRM packet will clarify about the cause of the failure
>
>
situation read access write access notes
unknown address DAT_UNKNOWN_ADDR_OUT DAT_UNKNOWN_ADDR_OUT ignore cycle, prepare for next access
entity is busy DAT_NO_MORE_DATA_OUT DAT_NO_MORE_DATA_OUT temporary error, retry must be possible
everything OK DAT_DATAREADY_OUT DAT_WRITE_ACK_OUT read data is OK, write data has been accepted
timeout DAT_TIMEOUT_IN DAT_TIMEOUT_IN ignore cycle, prepare for next access
 
Changed:
<
<
By this access handling we implement features similar to USB2.0 device endpoints (fatal errors yield in NAK, temporary errors with retry in NYET).
>
>
By this mechanism a broken entity on DAT_* bus can never lock up the slow control channel.
 
Changed:
<
<
This policy also forbids 1:1 translation of fast TRBnet accesses to slow bus systems in the endpoints (in case of RICH ADCM, direct TRBnet-to-I2C conversion). For such accesses polling has to be used to keep the dead time of the channel as low as possible.
>
>
-- MichaelBoehmer - 15 Dec 2008
 

Ports & Generics

Line: 79 to 77
 
DAT_DATA_OUT 32 write data
DAT_DATA_IN 32 read data
DAT_DATAREADY_IN 1 read data is valid
Added:
>
>
DAT_WRITE_ACK_IN 1 write data has been accepted
 
DAT_NO_MORE_DATA_IN 1 finish transfer / no more data
Added:
>
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DAT_UNKNOWN_ADDR_IN 1 unused address
DAT_TIMEOUT_OUT 1 endpoint timed out, access is broken
 

Generic Range Description
Revision 13
15 Dec 2008 - Main.MichaelBoehmer
Line: 1 to 1
 
META TOPICPARENT name="TrbNetEntities"

Reading and Writing registers over the network

TrbNetRegIO is a simple interface to read and write registers inside your application from anywhere on the network. The width of the registers is fixed to 32 Bit while 16Bit addresses are used.
Line: 11 to 11
 
60 7F   unused
80 BF internally writeable registers user defined status registers
C0 FF network writeable registers user defined control registers
Changed:
<
<
0100 FFFF data / address port forwarded to internal data port
>
>
0100 7FFF TRBnet space space reserved for TRBnet standardized functions
8000 FFFF data / address port forwarded to internal data port
 

Since it would cost to much resources to really implemented all the CTRL registers, one can select by setting generics how many registers should be used, which bits of the control registers are not used and what should be the initial state of the registers on startup.
Line: 42 to 43
 

The multiple access type is only available for the internal data port, not for reading registers. TrbNetRegIO then sets the read or write signal as many times as given in the request.
Added:
>
>

Access handling

TrbNetRegIO tries to handle all accesses to registers in a way which inhibits the "GTB effect". Accessing a non-existing register or an entitiy on the internal data bus which has deceased may under no circumstances lock up the channel.

The following rules are proposed to avoid deadlocks (names of non-existing signals are proposals only and subject to change):

  • all accesses on the internal data bus must be acknowledged
  • all accesses must be completed in a short period of time (128 100MHz clock cycles)
  • TrbNetRegIO implements a timeout counter for accesses to the internal data bus
  • user entities acknowledge valid register accesses with data transfer by DAT_DATAREADY_IN on reads and DAT_WRITEACK_IN on writes
  • in case of FIFOs (et al) where the register exists but has no data to send (read) or may not accept data (write) user entities use DAT_NO_MORE_DATA_IN (this gets translated to a short packet TRM in the endpoint)
  • in case of not existing registers user entities acknowledge by DAT_NOT_EXISTS_IN (this gets translated to a short packet TRM in the endpoint)
  • in case of DAT_NO_MORE_DATA_IN and DAT_NOT_EXISTS_IN error bits in the TRM packet will clarify about the cause of the failure

By this access handling we implement features similar to USB2.0 device endpoints (fatal errors yield in NAK, temporary errors with retry in NYET).

This policy also forbids 1:1 translation of fast TRBnet accesses to slow bus systems in the endpoints (in case of RICH ADCM, direct TRBnet-to-I2C conversion). For such accesses polling has to be used to keep the dead time of the channel as low as possible.
 

Ports & Generics

Revision 12
12 Dec 2008 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetEntities"

Reading and Writing registers over the network

TrbNetRegIO is a simple interface to read and write registers inside your application from anywhere on the network. The width of the registers is fixed to 32 Bit while 16Bit addresses are used.
Line: 31 to 31
 

Operation dtype F0 F1 F2 F3 Comment
multiple read 1010 ADDR Length   CRC?  
Changed:
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<
multiple write 1011 ADDR Data CRC?  
>
>
multiple write 1011 ADDR Config*   CRC?  
 
    res. Data CRC? repeated until all data is sent
Deleted:
<
<
When writing, the reply should be one data packet, containing status information. When reading, address and data is sent back. The length field gives number of 32Bit words that should be read. APL can finish earlier, for example when a fifo is empty.
 
Changed:
<
<
This access type is only available for the internal data port, not for reading registers. TrbNetRegIO then sets the read or write signal as many times as given in the request.
>
>

When writing, the reply is generated from a single read to the last address. When reading, address and data is sent back. The length field gives 15bit number of 32Bit words that should be read. APL can finish earlier, for example when a fifo is empty. The highest bit of the length field selects whether the address should be kept (0) or is continously counting up for each read (1).

Config(15) for the write access is the same as length(15) when reading: Enable signal for address counter.

The multiple access type is only available for the internal data port, not for reading registers. TrbNetRegIO then sets the read or write signal as many times as given in the request.
 

Ports & Generics

Revision 11
13 Oct 2008 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetEntities"

Reading and Writing registers over the network

TrbNetRegIO is a simple interface to read and write registers inside your application from anywhere on the network. The width of the registers is fixed to 32 Bit while 16Bit addresses are used.
Line: 21 to 21
 

A simple protocol is used to read and write into registers. For each operation, only one data packet is sent. In both cases, read and write, the reply contains again ADDR and Data.
Changed:
<
<
Operation dtype F1 F2 F3
single register read 1000 ADDR unused
single register write 1001 ADDR Data
replying to register access 1000 ADDR Data
>
>
Operation dtype F0 F1 F2 F3
single register read 1000 ADDR unused
single register write 1001 ADDR Data CRC?
replying to register access 1000 ADDR Data CRC?
 

To provide a dma-like memory access to access and transfer bigger amounts of data for example from a fifo, the memory read / write operations are used. The protocol is similar to the one for single register access:
Changed:
<
<
Operation dtype F1 F2 F3 Comment
multiple read 1010 ADDR Length    
multiple write 1011 ADDR    
    res. Data repeated until all data is sent
>
>
Operation dtype F0 F1 F2 F3 Comment
multiple read 1010 ADDR Length   CRC?  
multiple write 1011 ADDR Data CRC?  
    res. Data CRC? repeated until all data is sent
 

When writing, the reply should be one data packet, containing status information. When reading, address and data is sent back. The length field gives number of 32Bit words that should be read. APL can finish earlier, for example when a fifo is empty.
Line: 71 to 71
 

Changed:
<
<
-- JanMichel - 28 Mar 2008
>
>
-- JanMichel - 13 Oct 2008
 
Revision 10
08 Oct 2008 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetEntities"

Reading and Writing registers over the network

TrbNetRegIO is a simple interface to read and write registers inside your application from anywhere on the network. The width of the registers is fixed to 32 Bit while 16Bit addresses are used.

First Address Last Address Implementation Description
Changed:
<
<
0 31 internally writeable registers common status registers (CommonStatusRegister)
32 63 network writeable registers common ctrl registers (tbd)
64 71 ROM board information ROM
72 127 -- unused
128 191 internally writeable registers user defined status registers
192 255 network writeable registers user defined control registers
256 65535 data / address port forwarded to internal data port
>
>
00 1F internally writeable registers common status registers (CommonStatusRegister)
20 3F network writeable registers common ctrl registers (CommonStatusRegister#CommonControlRegister)
40 48 ROM board information ROM
50 5F RAM board information RAM (e.g. SubEvtId...)
60 7F   unused
80 BF internally writeable registers user defined status registers
C0 FF network writeable registers user defined control registers
0100 FFFF data / address port forwarded to internal data port
 

Since it would cost to much resources to really implemented all the CTRL registers, one can select by setting generics how many registers should be used, which bits of the control registers are not used and what should be the initial state of the registers on startup.
Revision 9
09 Apr 2008 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetEntities"

Reading and Writing registers over the network

TrbNetRegIO is a simple interface to read and write registers inside your application from anywhere on the network. The width of the registers is fixed to 32 Bit while 16Bit addresses are used.
Line: 29 to 29
  To provide a dma-like memory access to access and transfer bigger amounts of data for example from a fifo, the memory read / write operations are used. The protocol is similar to the one for single register access:

Operation dtype F1 F2 F3 Comment
Changed:
<
<
memory read 1010 ADDR  
    Length the number of 32Bit words that should be read. APL can finish earlier, for example when a fifo is empty
memory write 1011 ADDR  
>
>
multiple read 1010 ADDR Length    
multiple write 1011 ADDR    
 
    res. Data repeated until all data is sent
Changed:
<
<
When writing, the reply should be one data packet, containing status information. When reading, address and data is sent back. This access type is only available for the internal data port, not for reading registers. TrbNetRegIO then sets the read or write signal as many times as given in the request. If, on a read access, the application can not deliver more data, i.e. the fifo is empty, it sets the NO_MORE_DATA - signal to finish the transfer.
>
>
When writing, the reply should be one data packet, containing status information. When reading, address and data is sent back. The length field gives number of 32Bit words that should be read. APL can finish earlier, for example when a fifo is empty.

This access type is only available for the internal data port, not for reading registers. TrbNetRegIO then sets the read or write signal as many times as given in the request.
 

Ports & Generics

Revision 8
08 Apr 2008 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetEntities"

Reading and Writing registers over the network

TrbNetRegIO is a simple interface to read and write registers inside your application from anywhere on the network. The width of the registers is fixed to 32 Bit while 16Bit addresses are used.
Added:
>
>
First Address Last Address Implementation Description
0 31 internally writeable registers common status registers (CommonStatusRegister)
32 63 network writeable registers common ctrl registers (tbd)
64 71 ROM board information ROM
72 127 -- unused
128 191 internally writeable registers user defined status registers
192 255 network writeable registers user defined control registers
256 65535 data / address port forwarded to internal data port
 
Changed:
<
<

The addresses from 0 to 63 are status registers that can only be written from internal, addresses 64 to 128 can be written from over the network. Since it would cost to much resources if all these registers are really implemented, one can select by setting generics how many registers should be used, which bits of the control registers are not used and what should be the initial state of the registers on startup. The definitions of these registers is given in CommonStatusRegister.

The addresses from 128 to 256 are connected to the board information ROM.

The addresses from 256 on are forwarded to the internal data and address port.
>
>
Since it would cost to much resources to really implemented all the CTRL registers, one can select by setting generics how many registers should be used, which bits of the control registers are not used and what should be the initial state of the registers on startup.
 

Protocol

Changed:
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<
All accesses with dtype 1111 are given to TrbNetAddresses. This is used for address allocation only (at least at the moment)
>
>
All accesses with dtype 1111 are given to TrbNetAddresses. This is used for address allocation and readout of the unique ID.
 

A simple protocol is used to read and write into registers. For each operation, only one data packet is sent. In both cases, read and write, the reply contains again ADDR and Data.
Revision 7
01 Apr 2008 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetEntities"

Reading and Writing registers over the network

TrbNetRegIO is a simple interface to read and write registers inside your application from anywhere on the network. The width of the registers is fixed to 32 Bit while 16Bit addresses are used.
Changed:
<
<
The addresses from 0 to 63 are status registers that can only be written from internal, addresses 64 to 128 can be written from over the network. Since it would cost to much resources if all these registers are really implemented, one can select by setting generics how many registers should be used, which bits of the control registers are not used and what should be the initial state of the registers on startup.
>
>

The addresses from 0 to 63 are status registers that can only be written from internal, addresses 64 to 128 can be written from over the network. Since it would cost to much resources if all these registers are really implemented, one can select by setting generics how many registers should be used, which bits of the control registers are not used and what should be the initial state of the registers on startup. The definitions of these registers is given in CommonStatusRegister.

The addresses from 128 to 256 are connected to the board information ROM.
 

The addresses from 256 on are forwarded to the internal data and address port.

Protocol

Changed:
<
<
All accesses with dtype 1111 are given to TrbNetAddresses.
>
>
All accesses with dtype 1111 are given to TrbNetAddresses. This is used for address allocation only (at least at the moment)
 

A simple protocol is used to read and write into registers. For each operation, only one data packet is sent. In both cases, read and write, the reply contains again ADDR and Data.
Revision 6
31 Mar 2008 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetEntities"

Reading and Writing registers over the network

TrbNetRegIO is a simple interface to read and write registers inside your application from anywhere on the network. The width of the registers is fixed to 32 Bit while 16Bit addresses are used.
Deleted:
<
<

Addresses and Register types

The lowest 8 addresses are located inside a dual ported distributed ram. These registers can only be accessed in 16 16Bit blocks, not all in parallel like registers. These words are defined for all endpoints to allow a quick readout of basic status information from the whole network:
 
Changed:
<
<
Address Content
0 Unique ID - lower 32bit
1 Unique ID - higher 32bit
2 Unique ID - Board information
3 Endpoint Address
4 Status overview - tbd
5 tbd
6 tbd
7 tbd

The addresses from 128 to 191 are status registers that can only be written from internal, addresses 192 to 255 can be written from over the network. Since it would cost to much resources if all these registers are really implemented, one can select by setting generics how many registers should be used, which bits of the control registers are not used and what should be the initial state of the registers on startup.
>
>
The addresses from 0 to 63 are status registers that can only be written from internal, addresses 64 to 128 can be written from over the network. Since it would cost to much resources if all these registers are really implemented, one can select by setting generics how many registers should be used, which bits of the control registers are not used and what should be the initial state of the registers on startup.
 

The addresses from 256 on are forwarded to the internal data and address port.

Protocol

Added:
>
>
All accesses with dtype 1111 are given to TrbNetAddresses.
  A simple protocol is used to read and write into registers. For each operation, only one data packet is sent. In both cases, read and write, the reply contains again ADDR and Data.

Operation dtype F1 F2 F3
Line: 52 to 42
 
STAT_RAM_ADDRESS_IN 6 status ram address
STAT_RAM_DATA_IN 16 data to the status ram
STAT_RAM_DATA_OUT 16 data from the status ram
Added:
>
>
MY_ADDRESS_OUT 16 Trb_net_address of the endpoint
 
REGISTERS_IN 32*NUM_STAT_REGS connection for status registers
REGISTERS_OUT 32*NUM_CTRL_REGS connection for control registers
DAT_ADDR_OUT 16 internal address port
Line: 69 to 60
 
INIT_CTRL_REGS vector width: 2**NUM_CTRL_REGS*32 Init value for all control registers
USED_CTRL_REGS vector width: NUM_CTRL_REGS Which of the addressable register are used
USED_CTRL_BITMASK vector width: 2**NUM_CTRL_REGS*32 which of the bits of the used registers are used
Changed:
<
<
>
>
INIT_ADDRESS 16 Address, the endpoint should have on startup
INIT_UNIQUE_ID 96 The unique id on startup
 

Revision 5
28 Mar 2008 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetEntities"

Reading and Writing registers over the network

TrbNetRegIO is a simple interface to read and write registers inside your application from anywhere on the network. The width of the registers is fixed to 32 Bit while 16Bit addresses are used.
Line: 31 to 31
 
replying to register access 1000 ADDR Data
Changed:
<
<
A future option is forseen, to provide a dma-like memory access to access and transfer bigger amounts of data. The protocol is similar to the one for single register access:
>
>
To provide a dma-like memory access to access and transfer bigger amounts of data for example from a fifo, the memory read / write operations are used. The protocol is similar to the one for single register access:
 

Operation dtype F1 F2 F3 Comment
memory read 1010 ADDR  
Line: 39 to 39
 
memory write 1011 ADDR  
    res. Data repeated until all data is sent
Changed:
<
<
When writing, the reply will be one data packet, containing status information. When reading, address and data is sent back.
>
>
When writing, the reply should be one data packet, containing status information. When reading, address and data is sent back. This access type is only available for the internal data port, not for reading registers. TrbNetRegIO then sets the read or write signal as many times as given in the request. If, on a read access, the application can not deliver more data, i.e. the fifo is empty, it sets the NO_MORE_DATA - signal to finish the transfer.
 
Changed:
<
<
-- JanMichel - 27 Mar 2008
>
>

Ports & Generics

TrbNetRegIO connects to the network with a standard API-interface that is not shown here. The ports towards the application are as follows:

Port Width Description
STAT_RAM_WRITE_IN 1 write to the status ram
STAT_RAM_ADDRESS_IN 6 status ram address
STAT_RAM_DATA_IN 16 data to the status ram
STAT_RAM_DATA_OUT 16 data from the status ram
REGISTERS_IN 32*NUM_STAT_REGS connection for status registers
REGISTERS_OUT 32*NUM_CTRL_REGS connection for control registers
DAT_ADDR_OUT 16 internal address port
DAT_READ_ENABLE_OUT 1 internal read
DAT_WRITE_ENABLE_OUT 1 internal write
DAT_DATA_OUT 32 write data
DAT_DATA_IN 32 read data
DAT_DATAREADY_IN 1 read data is valid
DAT_NO_MORE_DATA_IN 1 finish transfer / no more data

Generic Range Description
NUM_STAT_REGS 0 - 6 Number of status registers is 2**NUM_STAT_REGS
NUM_CTRL_REGS 0 - 6 Number of control registers is 2**NUM_CTRL_REGS
INIT_CTRL_REGS vector width: 2**NUM_CTRL_REGS*32 Init value for all control registers
USED_CTRL_REGS vector width: NUM_CTRL_REGS Which of the addressable register are used
USED_CTRL_BITMASK vector width: 2**NUM_CTRL_REGS*32 which of the bits of the used registers are used

-- JanMichel - 28 Mar 2008
 
Revision 4
27 Mar 2008 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetEntities"

Reading and Writing registers over the network

TrbNetRegIO is a simple interface to read and write registers inside your application from anywhere on the network. The width of the registers is fixed to 32 Bit while 16Bit addresses are used.

Addresses and Register types

Changed:
<
<
Even if the address range is defined to be 16Bit wide, not all of these addresses can be connected to a register due to limited space. Thus only a specified range of addresses is connected to registers inside TrbNetRegIO while all other accesses are provided to the main application and can be handled there, for example to read out some external hardware on request or to access a Block RAM.
>
>
The lowest 8 addresses are located inside a dual ported distributed ram. These registers can only be accessed in 16 16Bit blocks, not all in parallel like registers. These words are defined for all endpoints to allow a quick readout of basic status information from the whole network:
 
Changed:
<
<
The registers are again divided into two parts: readonly and writeonly registers. The readonly registers can be written by the application and read from the network, the writeonly registers can be written from the network and read by the application. The address space is divided according to the following table:
>
>
Address Content
0 Unique ID - lower 32bit
1 Unique ID - higher 32bit
2 Unique ID - Board information
3 Endpoint Address
4 Status overview - tbd
5 tbd
6 tbd
7 tbd
 
Deleted:
<
<
start address end address purpose
0 2^(ADDRESS_USED_WIDTH-1)-1 read only registers (status registers)
2^(ADDRESS_USED_WIDTH-1) 2^(ADDRESS_USED_WIDTH)-1 writeonly registers (control registers)
2^(ADDRESS_USED_WIDTH) 2^16-1 treated by the application
 
Changed:
<
<
ADDRESS_USED_WIDTH is a generic of TrbNetRegIO. For example, if ADDRESS_USED_WIDTH = 3, the first 4 addresses are status registers, the next 4 are control registers and the remaining 65528 addresses are to be handled by the application. If these 65528 addresses are not used, the generic NO_DAT_PORT can be set to 1.
>
>
The addresses from 128 to 191 are status registers that can only be written from internal, addresses 192 to 255 can be written from over the network. Since it would cost to much resources if all these registers are really implemented, one can select by setting generics how many registers should be used, which bits of the control registers are not used and what should be the initial state of the registers on startup.
 
Changed:
<
<
If not all available CTRL registers are used, they can be switched off using USED_REGISTER_OUT to save resources. Additionally, if not all Bits of a CTRL register are used, they can be switched off individually using BITMASK_REGISTER_OUT. RESET_REGISTER_OUT sets the reset value for all CTRL registers.
>
>
The addresses from 256 on are forwarded to the internal data and address port.
 

Protocol

Changed:
<
<
A simple protocol is used to read and write into registers. For each operation, only one data packet is sent
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A simple protocol is used to read and write into registers. For each operation, only one data packet is sent. In both cases, read and write, the reply contains again ADDR and Data.
 

Operation dtype F1 F2 F3
single register read 1000 ADDR unused
single register write 1001 ADDR Data
replying to register access 1000 ADDR Data
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In both cases, the reply contains again ADDR and Data.
 
Changed:
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A future option is forseen, to provide a dma-like memory access to access and transfer bigger amounts of data. The protocol might look like this:
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A future option is forseen, to provide a dma-like memory access to access and transfer bigger amounts of data. The protocol is similar to the one for single register access:
 

Operation dtype F1 F2 F3 Comment
memory read 1010 ADDR  
Line: 39 to 41
 

When writing, the reply will be one data packet, containing status information. When reading, address and data is sent back.
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-- JanMichel - 28 Dez 2007

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-- JanMichel - 27 Mar 2008
 
Revision 3
28 Dec 2007 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetEntities"

Reading and Writing registers over the network

TrbNetRegIO is a simple interface to read and write registers inside your application from anywhere on the network. The width of the registers is fixed to 32 Bit while 16Bit addresses are used.
Line: 24 to 24
 
Operation dtype F1 F2 F3
single register read 1000 ADDR unused
single register write 1001 ADDR Data
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replying to register access 0000 ADDR Data
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replying to register access 1000 ADDR Data
 

In both cases, the reply contains again ADDR and Data.
Line: 40 to 40
  When writing, the reply will be one data packet, containing status information. When reading, address and data is sent back.
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-- JanMichel - 30 Nov 2007
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-- JanMichel - 28 Dez 2007
 

Revision 2
30 Nov 2007 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetEntities"

Reading and Writing registers over the network

TrbNetRegIO is a simple interface to read and write registers inside your application from anywhere on the network. The width of the registers is fixed to 32 Bit while 16Bit addresses are used.
Line: 15 to 15
 

ADDRESS_USED_WIDTH is a generic of TrbNetRegIO. For example, if ADDRESS_USED_WIDTH = 3, the first 4 addresses are status registers, the next 4 are control registers and the remaining 65528 addresses are to be handled by the application. If these 65528 addresses are not used, the generic NO_DAT_PORT can be set to 1.
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If not all available CTRL registers are used, they can be switched off using USED_REGISTER_OUT to save resources. Additionally, if not all Bits of a CTRL register are used, they can be switched off individually using BITMASK_REGISTER_OUT. RESET_REGISTER_OUT sets the reset value for all CTRL registers.
 

Protocol

Line: 40 to 40
  When writing, the reply will be one data packet, containing status information. When reading, address and data is sent back.
Changed:
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-- JanMichel - 28 Nov 2007
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-- JanMichel - 30 Nov 2007
 

 
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