Difference: TriggerLvl1Information (1 vs. 9)

Revision 9
27 Nov 2018 - Main.PeterZumbruch
Line: 1 to 1
 
META TOPICPARENT name="TrbNetUsersGuide"

LVL1 Trigger

Line: 16 to 16
 

  • When receiving a trigger acquire all data from the detector and store them in an internal memory until a query is received on the IPU / LVL2 channel.
Changed:
<
<
  • Count the incoming trigger strobes and compare this counter to the received trigger number. If there is a mismatch, set the appropriate bit in the error pattern and release the trigger. All necessary actions to resynchronize will be done by the CTS via SlowControl.
>
>
  • Count the incoming trigger strobes and compare this counter to the received trigger number. If there is a mismatch, set the appropriate bit in the error pattern and release the trigger. All necessary actions to resynchronize will be done by the CTS via DetectorControlSystem.
 

  • Watch the common control registers and reset your internal trigger strobe counter if the corresponding bit is set.
Revision 8
03 Nov 2009 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetUsersGuide"

LVL1 Trigger

Line: 32 to 32
 

  • 4 bit trigger code

Changed:
<
<
  • 8 spare bits for additional information
>
>
  • 24 bits for additional information (will be defined soon, Jan, 03.11.09)
 

Positions in the network packet are as follows:
Bits Content
Changed:
<
<
47 - 40 Additional Information
>
>
63 - 40 Additional Information
 
39 - 32 Random Data
31 - 16 16 bit counter
3 - 0 Trigger Type
Line: 69 to 69
 
TRG_TYPE_OUT 4 the old trigger code
TRG_NUMBER_OUT 16 trigger number
TRG_RANDOM_CODE_OUT 8 a random code to prevent "trigger number guessing"
Changed:
<
<
TRG_INFORMATION_OUT 8 spare bits for any kind of information
>
>
TRG_INFORMATION_OUT 24 spare bits for any kind of information
 
TRG_RECEIVED_OUT 1 rising edge signals received trigger and valid trigger data, falling edge comes one cycle after trg_release is high
TRG_RELEASE_IN 1 the busy release signal, should be set 'as soon as possible'
TRG_ERROR_PATTERN_IN 32 the standard error pattern
Revision 7
26 May 2009 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetUsersGuide"

LVL1 Trigger

Line: 69 to 69
 
TRG_TYPE_OUT 4 the old trigger code
TRG_NUMBER_OUT 16 trigger number
TRG_RANDOM_CODE_OUT 8 a random code to prevent "trigger number guessing"
Changed:
<
<
TRG_INFORMATION_OUT 32 spare bits for any kind of information
>
>
TRG_INFORMATION_OUT 8 spare bits for any kind of information
 
TRG_RECEIVED_OUT 1 rising edge signals received trigger and valid trigger data, falling edge comes one cycle after trg_release is high
TRG_RELEASE_IN 1 the busy release signal, should be set 'as soon as possible'
TRG_ERROR_PATTERN_IN 32 the standard error pattern
Revision 6
04 Feb 2009 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetUsersGuide"

LVL1 Trigger

Line: 41 to 41
 
31 - 16 16 bit counter
3 - 0 Trigger Type
Added:
>
>

Sending test-triggers via Etrax-FPGA-Interface

  A LVL1 "trigger" is sent by the following simple procedure:

  • write the error pattern to the corresponding 32bit register (see bit definitions below)
Revision 5
04 Feb 2009 - Main.MichaelBoehmer
Line: 1 to 1
 
META TOPICPARENT name="TrbNetUsersGuide"

LVL1 Trigger

Line: 41 to 41
 
31 - 16 16 bit counter
3 - 0 Trigger Type
Added:
>
>
A LVL1 "trigger" is sent by the following simple procedure:
 
Added:
>
>
  • write the error pattern to the corresponding 32bit register (see bit definitions below)
 
Added:
>
>
  • write trigger type to the start register (and don't forget the short transfer bit!)
 
Added:
>
>
  • done

An example: you want to sent trigger type 0xe, trigger number 0x1234, trigger random 0xab and trigger information 0xcd. So you have to write the error register (offset 0x112) with 0xcdab1234 first. Next write to start register with 0x0000010e will start the trigger transmission. Accessing the FIFO is not necessary.

Bit definition for error register:
Bits Content
31 - 24 Additional Information
23 - 16 Random Data
15 - 0 16 bit counter
 

Trigger receiver interface

Revision 4
31 Dec 2008 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetUsersGuide"

LVL1 Trigger

Line: 9 to 9
 

  • Each trigger strobe must be followed by an trigger information packet on the network before a new trigger strobe is sent. This is controlled by the CTS.
Changed:
<
<
  • The trigger release is sent as soon as possible, already when you know that you will be able to accept another trigger in a few microseconds.
>
>
  • The trigger release is to be sent as soon as possible, already when you know that you will be able to accept another trigger in a few microseconds.
 

Tasks for each endpoint

Line: 24 to 24
 

Data included in the LVL1 trigger packet

Changed:
<
<
The trigger data packet has space for 60 Bit of trigger information
>
>
The trigger data packet has space for 36 Bit of trigger information
 

  • a 16 bit counter

Line: 32 to 32
 

  • 4 bit trigger code

Changed:
<
<
  • 32 spare bits for additional information
>
>
  • 8 spare bits for additional information
 

Positions in the network packet are as follows:
Bits Content
Changed:
<
<
63 - 32 Additional Information
31 - 24 Random Data
23 - 16 Upper 8 bit of counter
12 - 4 Lower 8 bit of counter
>
>
47 - 40 Additional Information
39 - 32 Random Data
31 - 16 16 bit counter
 
3 - 0 Trigger Type
Revision 3
19 Dec 2008 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetUsersGuide"

LVL1 Trigger

Line: 9 to 9
 

  • Each trigger strobe must be followed by an trigger information packet on the network before a new trigger strobe is sent. This is controlled by the CTS.
Added:
>
>
  • The trigger release is sent as soon as possible, already when you know that you will be able to accept another trigger in a few microseconds.
 

Tasks for each endpoint

Line: 50 to 51
  The entity trb_net16_trigger provides an interface receive triggers and to release the trigger after processing has been finished.

Name Width Description
Changed:
<
<
TRG_TYPE_OUT 4  
TRG_NUMBER_OUT 16  
TRG_RANDOM_CODE_OUT 8  
TRG_INFORMATION_OUT 32  
TRG_RECEIVED_OUT 1  
TRG_RELEASE_IN 1  
TRG_ERROR_PATTERN_IN 32  
>
>
TRG_TYPE_OUT 4 the old trigger code
TRG_NUMBER_OUT 16 trigger number
TRG_RANDOM_CODE_OUT 8 a random code to prevent "trigger number guessing"
TRG_INFORMATION_OUT 32 spare bits for any kind of information
TRG_RECEIVED_OUT 1 rising edge signals received trigger and valid trigger data, falling edge comes one cycle after trg_release is high
TRG_RELEASE_IN 1 the busy release signal, should be set 'as soon as possible'
TRG_ERROR_PATTERN_IN 32 the standard error pattern
 
Changed:
<
<

-- JanMichel - 12 Sep 2008
>
>
-- JanMichel - 19 Dec 2008
 
Revision 2
27 Nov 2008 - Main.JanMichel
Line: 1 to 1
 
META TOPICPARENT name="TrbNetUsersGuide"

LVL1 Trigger

Line: 23 to 23
 

Data included in the LVL1 trigger packet

Changed:
<
<
The trigger data packet has space for 44 Bit of trigger information
>
>
The trigger data packet has space for 60 Bit of trigger information
 

  • a 16 bit counter

Line: 31 to 31
 

  • 4 bit trigger code

Changed:
<
<
  • 16 spare bits for additional information
>
>
  • 32 spare bits for additional information
 

Positions in the network packet are as follows:
Bits Content
Changed:
<
<
47 - 32 Additional Information
>
>
63 - 32 Additional Information
 
31 - 24 Random Data
23 - 16 Upper 8 bit of counter
12 - 4 Lower 8 bit of counter
Line: 53 to 53
 
TRG_TYPE_OUT 4  
TRG_NUMBER_OUT 16  
TRG_RANDOM_CODE_OUT 8  
Changed:
<
<
TRG_INFORMATION_OUT 16  
>
>
TRG_INFORMATION_OUT 32  
 
TRG_RECEIVED_OUT 1  
TRG_RELEASE_IN 1  
TRG_ERROR_PATTERN_IN 32  
 
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