Common Status Register

All network devices have one (or more) 32 Bit status registers. These registers will be read out for example once each second using TRBNet. This gives us the possibility to have one computer screen showing the overall status of the detector.

Additionally there are some status bits that are transported with every data transfer - These are merged ("wired-or") for all boards, so these contain some very rough information only. See TrbNetDatafields#Error_bits for details.

Bit Register 1 (Addr. 0x00) Register 2 (Addr. 0x01)
0 serious error* trigger_counter_lvl1
1 error* trigger_counter_lvl1
2 warning* trigger_counter_lvl1
3 info* trigger_counter_lvl1
4 trigger1_counter_mismatch* trigger_counter_lvl1
5 trigger2_counter_mismatch* trigger_counter_lvl1
6   trigger_counter_lvl1
7   trigger_counter_lvl1
8   trigger_counter_lvl1
9   trigger_counter_lvl1
10   trigger_counter_lvl1
11   trigger_counter_lvl1
12   trigger_counter_lvl1
13   trigger_counter_lvl1
14   trigger_counter_lvl1
15   trigger_counter_lvl1
16   trigger_counter_lvl2
17   trigger_counter_lvl2
18   trigger_counter_lvl2
19   trigger_counter_lvl2
20 temperature trigger_counter_lvl2
21 temperature trigger_counter_lvl2
22 temperature trigger_counter_lvl2
23 temperature trigger_counter_lvl2
24 temperature trigger_counter_lvl2
25 temperature trigger_counter_lvl2
26 temperature trigger_counter_lvl2
27 temperature trigger_counter_lvl2
28 temperature trigger_counter_lvl2
29 temperature trigger_counter_lvl2
30 temperature trigger_counter_lvl2
31 temperature trigger_counter_lvl2
*same as in Errorbits
  • The temperature is starting in the middle of a byte. This is done by purpose, since bits 20 to 23 represent the fractional part of the temperature.

Common Control Register

The first register contains strobe signals: All Bits are automatically cleared one clock cycle after they have been written to one. All other register keeps its data until another write process is done.

Bits [31:16] of the first register can be used to trigger a board by simple slow control accesses. This is mainly needed for the time where no TRBnet hubs / CTS is available for hardware designers working on the frontend endpoints (nag nag nag). Usage is optional.

The LVL1 trigger counter can be set by writing D[15:0] of offset 0x21. Reseting the trigger counter by D8 in offset 0x20 is depreciated! (Jan?)

Bit Register 0 (Addr. 0x20) Register 1 (Addr. 0x21)
0 Reset user logic 1 (frontends ?) trigger_counter_lvl1
1 Reset user logic 2 (trigger logic ?) trigger_counter_lvl1
2 Reset user logic 3 trigger_counter_lvl1
3 Reset user logic 4 trigger_counter_lvl1
4   trigger_counter_lvl1
5   trigger_counter_lvl1
6   trigger_counter_lvl1
7   trigger_counter_lvl1
8   trigger_counter_lvl1
9   trigger_counter_lvl1
10 Reset sequence counter trigger_counter_lvl1
11   trigger_counter_lvl1
12   trigger_counter_lvl1
13   trigger_counter_lvl1
14   trigger_counter_lvl1
15 reboot FPGA from FlashROM trigger_counter_lvl1
16 slow control trigger 0  
17 slow control trigger 1  
18 slow control trigger 2  
19 slow control trigger 3  
20 slow control trigger 4  
21 slow control trigger 5  
22 slow control trigger 6  
23 slow control trigger 7  
24 slow control trigger 8  
25 slow control trigger 9  
26 slow control trigger 10  
27 slow control trigger 11  
28 slow control trigger 12  
29 slow control trigger 13  
30 slow control trigger 14  
31 slow control trigger 15  

Board information ROM

There is an 8x16Bit RAM to store information of the board. Since trbnet registers are 32 bit wide, the odd numbered addresses are read out as the high word of the register before.

Register Address RAM Address Content (16Bit)
0x40 0 Compile time low word
  1 Compile time high word
0x41 2 Compile version
  3  
0x42 4 Hardware info 0
  5 Hardware info 1
0x43 6  
  7  
*also used for unique id

Detailed register map

The following addresses are currently used on all boards

Address Name Description
0x00 Common Status Register 0 Basic error flags, Temperature
0x01 Common Status Register 1 trigger counter values
0x20 Common Control Register 0 Strobes used for board resets and test triggers
0x21 Common Control Register 1 Common Control signals
0x22 Common Control Register 2 Set global time
0x40 Information ROM 0 Compile time
0x41 Information ROM 1 Design version
0x42 Information ROM 2 Hardware information
0x43 Information ROM 3 ---
0x50 Global Time Read global time
0x51 Time Since Trigger Read time since last timing trigger received
Topic revision: r18 - 19 Oct 2009, MichaelBoehmer
 
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