DTU in VHDL from Tiago

For debugging of the DTU check the DtuDebugRegisters page.

RPC-DTU debug registers

LVL1

DTU_DEBUG_11
DTU_DEBUG_12
DTU_DEBUG_13 = x"00"
DTU_DEBUG_14 = x"00"

DTU_DEBUG_11
7 6 5 4 3 2 1 0
ERR_IN_TRB 0 0 0 STATE LVL1

STATE LVL1 BUSY
IDLE 1 "0001" 0
decision_start 2 "0010" 1
running 3 "0011" 0
decision_trigtype 4 "0100" 1
check_tag_start 5 "0101" 1
check_tag 6 "0110" 1
error_1 7 "0111" 1
error_2 8 "1000" 1
error_3 9 "1001" 1
send_tag_start 10 "1010" 1
send_tag 11 "1011" 1
wait_ro 12 "1100" 1

DTU_DEBUG_12
7 6 5 4 3 2 1 0
BUSY DEADTIME ACK_TRB BUSY_TRB ERR 0 0 0 0

note: ACK_TRB is always '1'. It is not really needed.

LVL2

DTU_DEBUG_21
DTU_DEBUG_22
DTU_DEBUG_23 <= x"00"

DTU_DEBUG_24 <= x"00"

DTU_DEBUG_21: LVL2StateMachine
7 6 5 4 3 2 1 0
lvl2Counter(1,0) TRIGTAG(1,0) LVL2StateMachine

in the State Check_Tag_Start i registered both triggertag and triggercounter to compare in state CHECK_TAG.

LVL2StateMachine:
running "0001"
check_tag_start "0010"
check_tag "0100"
error_1 "1111"
send_tag_to_Fifo "1000"

DTU_DEBUG_22 : FIFO2DTU (read the DTu FIFO and send data to TRB)
7 6 5 4 3 2 1 0
fifo2dtu_State ACK_TRB_registered FIFO_FULL ACK_TRB

fifo2dtu_State
IDLE "10000"
READ_FIFO "01000"
FIFO_WAIT "01111"
FIFO_WAIT2 "01111"
FIFO_READY "00100"
ERROR_1 "11111"

-- TiagoPerez - 12 Nov 2005

-- MichaelTraxler - 09 Feb 2006
Topic attachments
I Attachment Action SizeSorted ascending Date Who Comment
LVL2stateMachine.pdfpdf LVL2stateMachine.pdf manage 11.9 K 16 Nov 2005 - 14:27 TiagoPerez LVL2 State Machine Bubble Diagram
LVL2state.pdfpdf LVL2state.pdf manage 12.2 K 16 Nov 2005 - 14:28 TiagoPerez LVL2 State Machine, connections.
LVL2stateFull.pdfpdf LVL2stateFull.pdf manage 12.3 K 16 Nov 2005 - 14:28 TiagoPerez LVL2 State machine Full
dtu.pdfpdf dtu.pdf manage 15.2 K 16 Nov 2005 - 14:25 TiagoPerez DTU SCHEMATIC
LVL2.pdfpdf LVL2.pdf manage 15.7 K 16 Nov 2005 - 14:30 TiagoPerez LVL2 Block Diagramm
TriggerBusInterface.pdfpdf TriggerBusInterface.pdf manage 19.6 K 16 Nov 2005 - 14:26 TiagoPerez Trigger Bus Interface (common lvl1 and lvl2
Topic revision: r2 - 12 Dec 2009, JanMichel
 
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