-- ChristophSchrader - 20 Mar 2007

Overview

* MAPS_BLOCK_SCHEMA.pdf: The illustration shows a block diagram of the typical configuration for the MAPS-readout device. The system consists of a proximity board, an auxiliary board, and an add-on board, which is connected to the TRB2. The proximity board serves as a support readout for the various versions of MAPS devices. This board is connected to an auxiliary board that adapts the individual signals required between the proximity board and the add-on-board. That means it converts the analog signals from the proximity board to differential signals, and the digital LVDS signals from the add-on-board to CMOS signals. It also provides the proximity board with a controlled power supply and contains digital and analog buffers to secure the transfer over long-distance cables to the add-on-board. The principal structure and function of the add-on-board is to control, collect, and process measuring data from the MAPS. See the functional description for a block diagram and further details about the functionality description of this board.

Add-on board design

* Addon_design_flussdiagramm.pdf: The add-on-board is connected to the rest of the MAPS system (auxiliary board) with a front-end interface. This interface groups the necessary signals to collect the data and to control the acquisition. The signals are divided between an analog front-end and a digital front-end. The analog front-end receives the analog signals and sets the analog offsets. The board comprises 4 analogue input signal channels, which deliver the analog measuring data from the MAPS by way of an Rj45 connector. The 4 ADC (for each matrix) convert the analog signals to 12-bit digital signals for the FPGA. These ADCs have a sampling frequency of up to 40 MHz. The digital front-end with low voltage differential signals (LVDS) is mainly used for clock distribution, such as ADC-clk and for signals that require minimal propagation delay. The data is processed in a FPGA device from Xilinx VIRTEX IV and the data are stored in 32 Meg x 16 of SDRAM organized in 2 memory banks. The board has also an DATA FIFO (Virtex) for data processing (see data processing). The FPGA VIRTEX IV is configured with an Etrax-FS processor unit, which is located on the TRB2 board. The data connection between TRB2 and the add-on-board is established with a connector. This firmware is configurable by Ethernet.

Addon board design ideas

This illustration shows a block diagram with the main ideas of the add-on-board, the TRB2 is in the background
* ADD_ON_board_Block_SCHEMA.pdf: addon board layout
* add_on_components.pdf: shows the components of the add-on
* power_supply.pdf: power of the components

schematics

* board_schematics.pdf: the board schematics and layout are constructed with Altium in the Uni-Frankfurt (in collaboration with Norbert Bialas, Stefan Schreiber)

PINOUT Tables and signal description

The block diagram shows the add on board with the connectors (PINOUT table). The specific signals are dedicated to the connectors.

* PIN_Blockschema.pdf: diagram of PINOUT table

The details and the description for the connectors and signals are in the following tables. It also shows the Pin configuration for the Virtex (only a draft proposal). At the moment 40 MHZ ADCs are used for MIMOSA, however for the next generations of MIMOSA-chips more MHZ is necessary.

* 26Pin-connector.pdf: 2x 26Pin-connector: The first 26Pin-connector is used for the clock distribution and the second is reserved for the MIMOSA 17 (in future).

* RJ45.pdf: meassurement-data-connector (RJ45): The RJ45 shows analog differential measurements data which will be shifted by 4 ADCs (AD9226) into digital signals. These will be processed by the Virtex.

* Add_ON_CON.pdf: addon connector (QSE): The addon connector is the connection between TRB2 and the add-on-board. It sends the MAPS measurements data to the TRB2. Also the connector delivers 5V as power supply, reset and the clock to the addon board. Furthermore it connects the ETRAX FS processor and slow-control functionality and the configuration for the Virtex.

* SDRAM_Table.pdf: 2x SDRAM table: The data are stored in 32 Meg x 16 of SDRAM organized in 2 memory banks

* Virtex_Table.pdf: Virtex table: A large FPGA (Xilinx Virtex4 XC4VLX-10FF1148) is placed on the board for data processing and controlling.

* JTESTCON.pdf: JTESTCON table: It is possible that on different parts of the board “Testconnentors for signal watching” is needed; those can be dropped out within the following boards.

data processing

Overview

The data processing is done by the FPGA with SDRAM and the internal FIFO from the Virtex. Therefore it is necessary, that the board has enough and well adapted hardwarespace to handle the data processing. The main tasks of the data processing are:
* correlated double sampling
* data compression
* threshold

* data_pipelining.pdf: Here is the overview of the data acquisition way. It works like a pipelining with fifos. The data input comes from the four ADCs which are parallel. The data are shifted through the loop until they come to the output. Thereby they move through some data operations. The advance of the pipelining is that no more time is needed for the data processing. So ADCs can deliver data without a brake. And also the dimension of the matrix is not relevant.

correlated double sampling

The difference between the reference value of the actual frame and of the frame before, offer a clear hit identification. For the subtraction you need two interne fifo and an SDRAM (see CDS in data_pipelining.pdf). The SDRAM is needed, because the fifo is too small for an complete frame. The SDRAM is used as a fifo and save the number of pixel for one complete frame. On the end of the second fifo is the same pixel as on the end of the first fifo, only a frame before. Now you can make out the difference between the pixels. The advance of the fifo looping is, that the fifos have just the dimension they need to buffer the data during the SDRAM is writing onto the second fifo.

data compression

Past the CDS we don't need such a high resolution, so we can reduce the date from 12 bit to 8 bit per pixel.

threshold (data selection)

* threshold.pdf: In the threshold there is a data selection. Here only the pixel with a hit and his direct neighbours are of interest. Therefore the data are shift through some fifos. In each of these coloured fifos is only one pixel, and in the blue fifos there are complete rows. If there is a hit listed the three single pixels go to the fifo downstairs. These are exactly the hit pixel and its 8 neighbours. Now the matrix is reduced to only a minimum of 9 pixels with the pointer information.
->The result is that not the complete matrix has to be read out, but only the hit pixel and its neighbours
Topic revision: r10 - 31 Dec 2009, JanMichel
 
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