TDC is connected with FPGA thru two interfaces:
  • JTAG
  • Parallel

JTAG interface

It is used for programming status register and control register of TDC's. To enable JTAG interface it has to be enabled in FPGA register.

./rwv2 w 0 6 1

After this coresponding lines are connected as below(part of VHDL code):
"...    TDC_TMS                        <= ETRAX_DATA_BUS_C(1);
        TDC_TCK                        <= ETRAX_DATA_BUS_C(2);
        TDC_TDI                        <= ETRAX_DATA_BUS_C(3);
        ETRAX_DATA_BUS_C(0)            <= TDC_TDO; ..."<BR>
TDC's are in JTAG chain. * JTAG chain:
JTAG chain

If one of the TDC's fail then it is possible by putting some jumpers(J24,25,26) and removing resistors(R113,114,115) to exclude this TDC from the chain.
For programming TDC and changing settings of TRB refer to the page TDCprogrammingViaJam

Parallel interface

This interface is used for downloading the data from the TDC.

-- MarekPalka - 28 Jun 2007

  • TDC readout(from hptdc manual):
    TDC readout

Topic attachments
I Attachment Action Size Date Who Comment
hptdc_manual_ver2.2.pdfpdf hptdc_manual_ver2.2.pdf manage 1415.5 K 28 Jun 2007 - 11:58 MarekPalka hptdc manual
jtagchain.jpgjpg jtagchain.jpg manage 25.2 K 28 Jun 2007 - 11:17 MarekPalka JTAG chain
tdcreadout.jpgjpg tdcreadout.jpg manage 75.1 K 28 Jun 2007 - 11:54 MarekPalka TDC readout
tdcwindows.jpgjpg tdcwindows.jpg manage 35.4 K 28 Jun 2007 - 11:47 MarekPalka Windows in TDC
Topic revision: r3 - 24 Jul 2007, MarekPalka
 
This site is powered by FoswikiCopyright © by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
Ideas, requests, problems regarding Hades Wiki? Send feedback
Imprint (in German)
Privacy Policy (in German)