Interface between Etrax and FPGA on TRB ("TrbNet edition")

Interface

The interface between Etrax and FPGA on the TRB2 uses 2 data ports (Port B and C) of the Etrax with 18 bit width each. Port B is an output of the FPGA and an input to the Etrax, Port C is used for the direction from Etrax to the FPGA.

The lower 16 bit always contain the payload of a transfer, while bit 16 used for controlling purposes:

PC(16) is a datavalid strobe from the Etrax a) to show that new data is presented on PC or b) Data presented on PortB by the FPGA has been read.

PB(16) is a datavalid signal from the FPGA: It is raised when new data is presented on PortB and lowered after a datavalid strobe from the Etrax has been received.

For PC(16) there is no exact timing, since we're running on a CPU, but the source code uses two nop's to guarantee a minimum pulse length to detect reliably by the FPGA.

The datavalids are set at the same time as the data bits. Data on PB must be valid from the rising edge of PC(16) until the rising edge of PB(16). If a datavalid from the FPGA is expected, the Etrax waits for 100 cycles of a loop checking PB(16) for it, then stops the access and exits with an error message.

Low Level Protocol

The protocol is a simple read/write to registers. The word size and the address size is 32 bit.

Write consists of six strobes from the Etrax:
  1. r/w-word: Bit 15 sets the mode of operation: 1 for read, 0 for write, the rest is don't care (at least for the trbnet-interface, the full etrax interface uses the lower bits to select the onboard devices)
  2. upper 16bit of address
  3. lower 16bit of address
  4. upper 16bit of data
  5. lower 16bit of data
  6. finally the FPGA sets its datavalid signal to acknowledge the write access and the Etrax answers with a final strobe

Read access:
  1. r/w-word: Bit 15 sets the mode of operation: 1 for read, 0 for write, the rest is don't care (at least for the trbnet-interface, the full etrax interface uses the lower bits to select the onboard devices)
  2. upper 16bit of address
  3. lower 16bit of address
  4. FPGA sets upper 16bit of data and datavalid, Etrax acknowledges with strobe
  5. FPGA clears datavalid, Etrax acknowledges
  6. FPGA sets lower 16bit of data and datavalid, Etrax acknowledges with strobe

Proposal: Use only a 16bit address with included read/write-select to access registers on this interface. There is no need to stay compatible with the address width of the DSP which is definitely not used on the CTS. This would save 40% of time for each access. Therefore, the first three steps are merged into a single word where Bit 15 sets the mdoe of operation (1: read, 0: write) and the other bits form a 15bit address.

Registers for TrbNet Access

The registers implemented for sending and receiving data over TrbNet are as follows.

Address Tye Name Description
1z0 write sender_control (3..0) dtype, (8) short transfer
1z1 write target_target target address
1z2 write sender_error Error pattern
1z3 write sender_data Fifo for data to be sent
1z4 read sender_fifo_status (9..0) data count, (16) fifo full, (17) fifo empty
1zF read sender_status (0) transfer running
2z3 read receiver_data Fifo for received data
2z4 read receiver_fifo_status (9..0) data count, (16) fifo full, (17) fifo empty
3z0 read api_status (7..0) sequence number

  • The lowercase z replaces the channel number times two plus 1 (for active transfers, 0 for passive transfers which are not used)

  • The fifo data contains bits 2 and 0 of the packet number using bits 17 and 16. Bit 24 is 1 when a valid read from the fifo has been done.

  • Sending of data is started, when register 1z0 is written.

  • Currently there is no support for transfers bigger than 1000 16bit words!

  • Received data contains the full trbnet packet, with packet start and four words with data
-- JanMichel - 19 Dec 2008
Topic revision: r3 - 29 Jun 2012, JanMichel
 
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