-- KrzysztofKorcyl - 19 Sep 2005

RPC board CALIBRATION

Calibration, according to NASA definition, is the process of collecting instrument characterization information (scale, offset, nonlinearity, operational, and environmental effects), using either laboratory standards, field standards, or modeling, which is used to interpret instrument measurements (ie, "data calibration").

Calibration of the RPC board mainly focuses on impact of the RPC layout (crosstalk between paths, noise from power supply, grouding,etc.) on performance of the HPTDC chips. As the HPTDC chips are also subject to calibration (see later), the RPC board calibration characterizes the RPC board as a whole including calibration of the HPTDC chips to produce optimal results (minimal measurement errors).

Calibration is of the HPTDC chips refers to a process of setting the DLL_adjust bits to get the smallest non-linearities: differential and integral. This is worth doing for both the high precision and the very high precision modes (consult page 69 of the HPTDC manual). For the very high precision mode one needs in addition to adjust bits in the RC delay line for the four registers used by the on-chip interpolator. Calibration of the RC line is relatively simple and the calibration process is described in the HPTDC manual in page 45 (chapter 18). Some explanation on what differential and integral nonlinearities do mean can be consulted with the following picture (I suggest to open that picture in a separate window to consult it with the explanation text below).

The TDC nonlinearity measurements are performed using code density test. Such test is based on delivering to the TDC a large number of hits (say 5Mio - to get significant statistics) from some uncorrelated source. If we then histogram recorded times (taken modulo 25.6ns: what means 256 channels in high precision settings or 8 LSB bits) we should see equal contents (within the statistical significance) in all bins of the histogram. For an ideal TDC. Some of the discrepances can be quantified by nonlinearities of the chip. The differential nonlinearity represents difference between the actual histogram bin contents of the two adjacent bins. This difference is normalized to the expected contents of a bin (to express nonlinearity as a fraction of the LSB). The example of the differential nonlinearity for our board and one of the TDC chips operating in high precision mode (1 LSB = 100 ps) is presented in this picture. The two lines plotted in the picture represent differential nonlinearity for two sets of the DLL taps. One “zero” was obtained for the all DLL tap bits set to “0”. The “recommended” was obtained after the TDC were programmed with values for the DLL_tap bits recommended by the HPTDC manual. Currently we do not have a better settings for the DLL taps – we use recommended.

The integral nonlinearity represents deviation between the time calculated using the TDC transfer function at any given TDC’s digital output and an actual time at which this digital number shows up at the TDC’s output. The transfer function should be linear. There are two possibilities to define this function. One uses the best fit to the measurements taken at all digital outputs. The other one is the ideal transfer function – is assumes that change in LSB at any given TDC’s output is caused by a change in time by 100 ps. The first approach shows only nonlinearity as it uses “real” TDC characteristics. The second one shows in addition all other errors (like offset) – as it uses “ideal” TDC transfer function. The example of the integrated nonlinearity for our board and one of the TDCs operating in high precision mode in presented in this picture. The four lines plotted there present integrated nonlinearity for the two functions: the “best fit” and “expected”. The "best fit" function was obtained by converting the code density test histogram into the accumulated histogram (hence the title of the plot), where number of entries in each bin is a sum of entries from all bins from the beginning up to the given bin. The "expected" function represents ideal transfer function and was obtained from accumulated histogram with "ideal" number of entries. The integrated nonlinearities were calculated for two different sets of DLL bits: all bits set to “0” (zeroed) or the bits were set to values recommended by the HPTDC manual (recommended). Currently we use recommended values – as there was no attempt to look for any better settings.

The complete results from the code density tests and the nonlinearities calculation can be viewed in the following excel spreadsheet

-- MichaelTraxler - 28 Jan 2009
Topic attachments
I Attachment Action Size Date Who Comment
ADCnonlinearities.pngpng ADCnonlinearities.png manage 212.2 K 06 Sep 2005 - 15:41 KrzysztofKorcyl ADC nonlinearities
calibrDLL.xlsxls calibrDLL.xls manage 376.5 K 19 Sep 2005 - 09:07 KrzysztofKorcyl calibration data from code density tests
differentialNonlinearity.pngpng differentialNonlinearity.png manage 8.1 K 07 Sep 2005 - 13:31 KrzysztofKorcyl differential nonlinearity
integratedNonlinearity.pngpng integratedNonlinearity.png manage 10.9 K 19 Sep 2005 - 08:43 KrzysztofKorcyl intergrated nonlinearity
Topic revision: r1 - 28 Jan 2009, MichaelTraxler
 
This site is powered by FoswikiCopyright © by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
Ideas, requests, problems regarding Hades Wiki? Send feedback
Imprint (in German)
Privacy Policy (in German)