-- MarekPalka - 02 Mar 2007

MarekPalka

Main tasks are:

  • Crosstalk(CrossTalk) and nonlinearity - TDC calibration started ,
  • Implement internal registers to write to from Etrax:
    • Changing delay of trigger, which is sending to TDC, done
    • Enable/disable direct trigger - without or with Hades trigger bus, done
    • Enable/disable bunch reset after every event or between spill done
  • Generate digital trigger to readout of TDCs by the "T" signal on the Trigger bus, don't wait till the whole trigger tag has been transferred
  • VHDL code for 2GBit transceivers 64 bit -> ( <- ) 16bit test:
    • small test done with 16 bit transmition: memory with random data was send thru optical link done
    • link_converter.vhd - 64 - > 16 bit (16 bit -> 64 bit) simulation done
    • link_converter.vhd - 64 - > 16 bit (16 bit -> 64 bit) hardware application done .
  • I2C for the SPFs
    • simulation done
    • hardware tests started
  • New TRB V2 VHDL code almost finished . Entities:
    • tdc_interface.vhd almost finished (has been simulated and tested)
    • lvl1_fifo.vhd done (has been simulated and tested)
    • lvl1_lvl2_busy.vhd - almost finished (has been simulated and tested)
    • trigger_logic.vhd - almost finished (has been simulated and tested)
    • etrax_interface.vhd - almost finished (has been simulated and tested)
    • tlk_interface.vhd - almost finished (has been simulated and tested)
    • dsp_interface.vhd - started (it is possible to write and read from the DSP
    • dtu_interface.vhd - almost finished
    • sdram_interafce.vhd - started - it is possible to write and read (problems with addressing), no burst, still under tests
    • connection with mdc addon - started - it was possible to see some unreal data (self triggering mode - I'm treating mdc addon as TDC's on TRB - send token and wait for data)
    • ctu.vhd - started - code is written, now I have to test it...
    • other entities (SPI...)
    • actual situation:
      • it was possible to read TDC ID and program with setup data, there is error in JTAG interface - this is not destroying the data(jtag interface error) .. ,
      • optical transmition is ok,
      • together with Radek we wrote comunication protocol and it is working
      • All VHDL programs were connected, it was possible to download the data from the TDC's with ETRAX(Radek's part) and with included HADES DAQ(Radek's part)
      • Whole code needs to be cleaned and corrected (e.g. IO register in synplify)
        It was possible to achieve:
10 kHz with 80 words per event (apr. 40kHz with 20 words per event)
  • Communication protocol between ETRAX-FS and FPGA done
  • MU V2:
    • hardware: MU concentrator, 1.5 GBit link - optical link test started
    • software: MU algorithm - same as old MU, but in VME-CPU not started
  • TRB V1 tests of all channels started (test setup - JIN1 LVTTL on pin 9, JOUT1 4th pair)
  • TRB network - some cosmetics needed - started
  • Changing htrbbaseupacker.cc (new header) - started - needs verification with hld file with new data format
Topic revision: r5 - 27 Jun 2007, MarekPalka
 
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