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BookkeepingPadiwa
Padiwa and PadiwaAmps1 bookkeeping Padiwa PadiwaAMPS Serial Number current location Patch A Patch B FPGA design comment 1 D Lab ECAL ...
CrossTalk
Main.MarekPalka 16 Nov 2006 On the picture below is presented crosstalk measured on 2 channels. On one channel is pulse which is about 55ns wide. Disturbing chan...
CypressPart
Main.MarekPalka 29 May 2006 Cypress registers
DAQManualShort
A short version of the DAQ manual. This is a working version of the document, if you see some changes in the startup procedure feel free to update this page. To s...
DaqUpgradeOverview
DAQ Upgrade This document gives an overview of why and how we want to upgrade our HADES DAQ/Trigger System. The upgrade at a glance : ) . Motivation for an Upgr...
DescriptionOfFPGA
A VIRTEX4 LX40 FPGA is used on the TRBv2. FPGA registers r/w adress bits r 0 31 26 not used ADO_LV 25 0 r 1 31 lvl2 busy 30:lvl1_fif...
DescriptionOfTDC
TDC is connected with FPGA thru two interfaces: * JTAG * Parallel JTAG interface It is used for programming status register and control register of TDC's...
JamProgramming
Main.MarekPalka 29 May 2006 How to programm Cypress jam p0xb5200000 aCONFIGURE_DEVICE cy_top.stp Programm board with base 0xb. rw w 0xb5200004 90 for Cypress ...
MatchingUnitV2
Main.MarekPalka 29 May 2006 * XilinxPart * CypressPart * JamProgramming
NewCTS
CTS and Trigger Logic addresses To all register when accessing vi trbnet add offset A0 CTS Address Bit range Meaning 91 15 downto 0 lvl1 trigger number...
NewProtocolEtraxToFPGA
Main.MarekPalka 02 Nov 2006 Port C7 0 is used as an output of Etrax and port C15 8 is used as input. With first trigger etrax sends what kind of action(M) i...
RPCMinutesMeeting20050524
Minutes of TRB Meeting 2005 05 31 Attendees: Wolfgang Koenig, Marcin Kajetanowicz, Ingo Frhlich, Michael Traxler, Piotr Salabura, Jerzy Pietraszko Topics: Sta...
SpeedImprovement
Current speed: 1000 Event/sec goal: 5000 Event/sec check waitstates waitstates application: Results: * speed the application with empty loop (it ...
TDCReadoutBoard
TRB (TDC Readout Board for RPC and other tasks) Direct Link to TRBv3 New (Jan. 2011) development for TDC applications TDCReadoutBoardV3 Direct Link to TRBv2 T...
TDCReadoutBoardV2Beam2012
When restart of the DAQ and reprogramming of the FPGAs does not help First try to login to etraxpXXX Check if the home directory (ls /home/hadaq/) on the Etrax is...
TDCprogrammingViaJam
How to generate jam and tcl files In view of growing number of TRBs the make.pl perl script was made to produce jam files with TDC settings and channels enabled/d...
TRBBoardStatus
Here the TRB Version 1 are listed where they are used and their current status de etrax where status additional information last update 001 cracow Ok ...
TRBProgressReports
Radek TIPS about DAQ, kernel, etc. manual about DAQ readout scripts TRBvIIHowTo for trb v2 AnaSimMay07 1 Quantum Mechanic very well ...
TRBPublicationList
TRB Publication List Here we should collect all available presentations/talks/papers Please also put all information about location and date. 2006 * TRBv2_Sc...
TRBUseDocumentation
Main.MichaelTraxler 22 Nov 2005 CPLD on board configuration The usage of CPLD is involved with SWITCH2 and also with register in FPGA. Vi this CPLD we can progra...
TRBvIIHowTo
How to use the TRBv2 * How to start * How to start readout * DescriptionOfEtrax * DescriptionOfFPGA * DescriptionOfTDC Main.MarekPalka 27 Jun 2...
VULOM3Triggerbox
Level 1 trigger processing by VULOM3 board The old triggerbox has now been replaced by an FPGA module and can be remotely controlled by EPICS. Here is provided so...
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XilinxPart
Main.MarekPalka 29 May 2006 Xilinx registers Address 0x0: bits 7 6 5 4 3 2 1 0 TDO of jtag port CY_config_done pin status ...
Number of topics: 25
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