Here we describe our various AddOn Cards for the TRBv2

ShowerAddOn

The features of the ShowerAddOn alias General-Purpose-ADC-AddOn

  • 96 channels 10-bit ADCs
  • 40/60 MSPS
  • ADC type: AD9212 from Analog Devices
  • low noise, variable gain amplifier at the input (AD8334 from Analog Devices)
  • input voltage range: ± 275 mV (AC coupled),
  • -3 dB bandwidth: 100 MHz (independent on gain)
  • amplifier noise: 0.74 nV/sqrt(Hz), 2.5 pA/sqrt(Hz)

  • Two 68-pin connectors, each connector contains:
    • 48 analog inputs,
    • 5 LVDS lines (programmable direction)
    • 2 TTL lines (programmable direction)
    • +5V (2 pins), GND (6 pins).
    • Connector type: HDRA-EC68LFDT-SL from Honda Connectors

FPGA: LFE2-70E-5F900C from Lattice

Up to now (2007-09-13), a schematics is existing.

The General Purpose Add on: Short Description

The General Purpose Add on (GP-AddOn) board povides the interface between the TRBv2 (main readout board) and many different signals. For example it can used as interface to the old HADES trigger bus. The GP-AddOn can be easily connected to the TRBv2 board through 2 connectors (QSE-040-01) placed on the back side of the board. The power supply is given to the GP-Addon through the connector's pins. A programmable logic CPLD ( XCR3128XL7VQ100C) is placed on the right hand side and is supported by Xilinx Web-PACK™ and industry standard CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor, Synopsys, Viewlogic, and Synplicity), using HDL editors with ABEL, VHDL, and Verilog. Design verification uses industry standard simulators for functional and timing simulation. Here we attach the data sheets for further details of the board's component:

General Purpose addon board: front view
GPAddon

General Purpose addon board: back view
GPAddon

General Purpose addon board: block diagram
GPAddon

Connector A (JADDON1)

With these connectors (JADDON1 and JADDON2) the Add-on board communicates with the TRBv2 board: it receives trigger information and basically it sends data to TRBv2. In this connector we use ONLY LVDS signals between addon-board and TRB.

Pin Name Pos/Neg Direction
1 ADO_LV0 P I/O
2 ADO_LV28 P I/O
3 ADO_LV1 N I/O
4 ADO_LV29 N I/O
5 GND  
6 GND  
7 ADO_LV2 P I/O
8 ADO_LV30 P I/O
9 ADO_LV3 N I/O
10 ADO_LV31 N I/O
11 GND  
12 GND  
13 ADO_LV4 P I/O
14 ADO_LV32 P I/O
15 ADO_LV5 N I/O
16 ADO_LV33 N I/O
17 GND  
18 GND  
19 ADO_LV6 P I/O
20 ADO_LV34 P I/O
21 ADO_LV7 N I/O
22 ADO_LV35 N I/O
23 GND  
24 GND  
25 ADO_LV8 P I/O
26 ADO_LV36 P I/O
27 ADO_LV9 N I/O
28 ADO_LV37 N I/O
29 GND  
30 GND  
31 ADO_LV10 P I/O
32 ADO_LV38 P I/O
33 ADO_LV11 N I/O
34 ADO_LV39 N I/O
35 GND  
36 GND  
37 ADO_LV12 P I/O
38 ADO_LV40 P I/O
39 ADO_LV13 N I/O
40 ADO_LV41 N I/O
     
P1 5 V  
P2 5 V  
P3 5 V  
P4 5 V  
     
41 ADO_LV14 P I/O
42 ADO_LV42 P I/O
43 ADO_LV15 N I/O
44 ADO_LV43 N I/O
45 GND  
46 GND  
47 ADO_LV16 P I/O
48 ADO_LV44 P I/O
49 ADO_LV17 N I/O
50 ADO_LV45 N I/O
51 GND  
52 GND  
53 ADO_LV18 P I/O
54 ADO_LV46 P I/O
55 ADO_LV19 N I/O
56 ADO_LV47 N I/O
57 GND  
58 GND  
59 ADO_LV20 P I/O
60 ADO_LV48 P I/O
61 ADO_LV21 N I/O
62 ADO_LV49 N I/O
63 GND  
64 GND  
65 ADO_LV22 P I/O
66 ADO_LV50 P I/O
67 ADO_LV23 N I/O
68 ADO_LV51 N I/O
69 GND  
70 GND  
71 ADO_LV24 P I/O
72 ADO_LV52 P I/O
73 ADO_LV25 N I/O
74 ADO_LV53 N I/O
75 GND  
76 GND  
77 ADO_LV26 P I/O
78 ADO_LV54 P I/O
79 ADO_LV27 N I/O
80 ADO_LV55 N I/O
     
P5 GND  
P6 GND  
P7 GND  
P8 GND  

IN/OUT - direction seen from add-on board

Connector B (JADDON2)

Pin NameSorted descending Comments
53 GND  
55 GND  
61 GND  
67 GND  
73 GND  
79 GND  
P5 GND  
P6 GND  
P7 GND  
P8 GND  
64 FS_PE9 LVTTL I/O
62 FS_PE8 LVTTL I/O
60 FS_PE7 LVTTL I/O
58 FS_PE6 LVTTL I/O
56 FS_PE5 LVTTL I/O
54 FS_PE4 LVTTL I/O
52 FS_PE3 LVTTL I/O
50 FS_PE2 LVTTL I/O
80 FS_PE17 LVTTL I/O
78 FS_PE16 LVTTL I/O
76 FS_PE15 LVTTL I/O
74 FS_PE14 LVTTL I/O
72 FS_PE13 LVTTL I/O
70 FS_PE12 LVTTL I/O
68 FS_PE11 LVTTL I/O
66 FS_PE10 LVTTL I/O
48 FS_PE1 LVTTL I/O
46 FS_PE0 LVTTL I/O
75 ADON_CLK LVDS P IN
77 ADON_CLK LVDS P IN
19 ADO_TTL9 LVTTL I/O
17 ADO_TTL8 LVTTL I/O
15 ADO_TTL7 LVTTL I/O
13 ADO_TTL6 LVTTL I/O
11 ADO_TTL5 LVTTL I/O
49 ADO_TTL46 LVTTL I/O TMS
47 ADO_TTL45 LVTTL I/O TDI
45 ADO_TTL44 LVTTL I/O TCK
43 ADO_TTL43 LVTTL I/O TDO
41 ADO_TTL42 LVTTL I/O
44 ADO_TTL41 LVTTL I/O
42 ADO_TTL40 LVTTL I/O
9 ADO_TTL4 LVTTL I/O
40 ADO_TTL39 LVTTL I/O
38 ADO_TTL38 LVTTL I/O
36 ADO_TTL37 LVTTL I/O
34 ADO_TTL36 LVTTL I/O
32 ADO_TTL35 LVTTL I/O
30 ADO_TTL34 LVTTL I/O
28 ADO_TTL33 LVTTL I/O
26 ADO_TTL32 LVTTL I/O
24 ADO_TTL31 LVTTL I/O
22 ADO_TTL30 LVTTL I/O
7 ADO_TTL3 LVTTL I/O
20 ADO_TTL29 LVTTL I/O
18 ADO_TTL28 LVTTL I/O
16 ADO_TTL27 LVTTL I/O
14 ADO_TTL26 LVTTL I/O
12 ADO_TTL25 LVTTL I/O
10 ADO_TTL24 LVTTL I/O
8 ADO_TTL23 LVTTL I/O
6 ADO_TTL22 LVTTL I/O
4 ADO_TTL21 LVTTL I/O
2 ADO_TTL20 LVTTL I/O
5 ADO_TTL2 LVTTL I/O
39 ADO_TTL19 LVTTL I/O
37 ADO_TTL18 LVTTL I/O
35 ADO_TTL17 LVTTL I/O
33 ADO_TTL16 LVTTL I/O
31 ADO_TTL15 LVTTL I/O
29 ADO_TTL14 LVTTL I/O
27 ADO_TTL13 LVTTL I/O
25 ADO_TTL12 LVTTL I/O
23 ADO_TTL11 LVTTL I/O
21 ADO_TTL10 LVTTL I/O
3 ADO_TTL1 LVTTL I/O
1 ADO_TTL0 LVTTL I/O
65 ADO_LV59 LVDS N OUT
63 ADO_LV58 LVDS P OUT
59 ADO_LV57 LVDS N I/O
57 ADO_LV56 LVDS P I/O
69 ADO_CLKOUT LVDS P OUT
71 ADO_CLKOUT LVDS N OUT
51 ADDON_RESET LVTTL IN
P1 5 V  
P2 5 V  
P3 5 V  
P4 5 V  
     
     
     

IN/OUT - direction seen from add-on board

Trb-Net media naming convention

The 31 GP LVDS lines plus the CLK line (only input in the Virtex4) will be the LVDS media for the NewTriggerBus. To avoid confusion, the assignment is given in this table:
LVDS pair on the schematics Official Name Direction
ADO_LVDS0,1 LVDS0 TRB to Acromag
...
ADO_LVDS30,31 LVDS15 TRB to Acromag
ADO_LVDS32,33 LVDS16 Acromag to TRB
ADO_LVDS34,35 LVDS17 Acromag to TRB
ADO_LVDS36,37 LVDS18 Acromag to TRB
ADO_LVDS38,39 LVDS19 Acromag to TRB
ADO_CLKOUT(p) LVDS20 Acromag to TRB
ADO_LVDS40,41 LVDS21 Acromag to TRB
...
ADO_LVDS60,61 LVDS31 Acromag to TRB

MDC Add-on Board: ERNI Connector(LVL1 bus)

With these connectors the MDC Add-on board communicates with the Motherboards placed on the MDC frame: it configures the TDCs on the Motherboards (through the CPLDs) and collects data.

Pin Name Direction Comment
1 TDZ   JTAG
2 TDA   JTAG
3 TMS   JTAG
4 TCK   JTAG
5 RES Out Mode device reset
6 TOK Out Mode token
7 MOD Out Mode select
8 WRM Out Mode-Write
9 GDE+ Out GDE+ Inhibit(global disable)
10 GDE- Out GDE- Inhibit(global disable)
11 AOD+ I/O Address or Data
12 AOD- I/O Address or Data
13 RDO+ In Ready from last Hamot
14 RDO- In Ready from last Hamot
15 CMS+ Out Common Stop output
16 CMS- Out Common Stop output
17 DST+ I/O Data Strobe I/O
18 DST- I/O Data Strobe I/O
19 ACK+ I/O Acknowledge
20 ACK- I/O Acknowledge
21 ADSO In Board Address input
22 NCO ??? Spare
23 ADS1 In Board Address input
24 NC1 ??? Spare
25 ADS2 In not used
26 NC2 ??? Spare
27 OR+ In Common Or input
28 OR- In Common Or input
29 RDM+ Out Ready to first Hamot
30 RDM- Out Ready to first Hamot
31 AD 00+ I/O Address/Data
32 AD 00- I/O Address/Data
33 AD 01+ I/O Address/Data
34 AD 01- I/O Address/Data
35 AD 02+ I/O Address/Data
36 AD 02- I/O Address/Data
37 AD 03+ I/O Address/Data
38 AD 03- I/O Address/Data
39 AD 04+ I/O Address/Data
40 AD 04- I/O Address/Data
41 AD 05+ I/O Address/Data
42 AD 05- I/O Address/Data
43 AD 06+ I/O Address/Data
44 AD 06- I/O Address/Data
45 AD 07+ I/O Address/Data
46 AD 07- I/O Address/Data
47 AD 08+ I/O Address/Data
48 AD 08- I/O Address/Data
49 RSV+ ??? (I/O) reserve
50 RSV- ??? (I/O) reserve

IN/OUT - direction seen from add-on board

Pinout of the transceivers placed on the ROC board:

Two of 75976A2 transceivers are connected to one ERNI connector. In the first row there are the enable signals (6) and in the column the name of the corresponding pins.

REN ENR   ENB   DRB   DRA   DRE
RSV GDE   AOD   RDO   ACK   AD01
  RDM   DST   OR       AD02
  CMS               AD03
                AD04
                AD05
                AD06
                AD07
                AD08
                AD09

-- AttilioTarantola - 09 Oct 2006
Topic attachments
I Attachment Action Size Date Who Comment
general_porpouse_addon.gifgif general_porpouse_addon.gif manage 56.5 K 23 Jul 2007 - 15:47 AttilioTarantola general porpouse addon block diagram
gp_addon_back.jpgjpg gp_addon_back.jpg manage 2382.9 K 25 Jul 2007 - 19:51 AttilioTarantola GP-AddOn back
gp_addon_front.jpgjpg gp_addon_front.jpg manage 2432.9 K 13 Jul 2007 - 12:56 AttilioTarantola General purpose addon board
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Topic revision: r19 - 13 Sep 2007, MichaelTraxler
 
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