-- MichaelTraxler - 22 Nov 2005

CPLD on board configuration

The usage of CPLD is involved with SWITCH2 and also with register in FPGA. Vi this CPLD we can programm FPGA and TDC's and also send test signal synchronized with trigger.

- Position 0 - 7: the test signal for RPC is enabled and only individual chips (FPGA, TDCA-D) can be programmed.

  1. to program FPGA
  2. to program TDCA
  3. to program TDCB
  4. to program TDCC
  5. to program TDCD

- Position 8 - F: the test signal is diabled and we can choose the TDC or FPGA to programm it from Etrax interface - PB(2),PB(1),PB(0) lines. The configuration of bits is as before.

  • FPGA
- To enable(1) or disable(0) test signal we have to write from Etrax to FPGA register. This register is at 74 address.
./rw w 74 0|1

List of thigs which should be prepared, taken and done before assembling whole TRB system outside the GSI

- Cables for 8930E-080178-MS connector. TDC LVDS signals - four cables,
- Cables for ZF5-20-01 connector (JTL). Two cables and two spare,
- Power supply: 48 V min 0.5 A current ,
- Power supply cable,
- Generator for trigger without HADES bus and for tests,
- diff -> LVDS convertor (build by Michael),
- Cables from generator to JTL connector. From output of generator to JTL connector - 2 signals (test, trigger),
- Ethernet cable,
- Minicom cable,
- Prepere NFS,
- Prepere cernel for etrax,
- Copy everything from GSI etrax NFS .
Topic revision: r2 - 14 Jul 2006, MarekPalka
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