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DescriptionOfEtrax
spi for Tof This site is still waiting for Marek :)
DescriptionOfFPGA
A VIRTEX4 LX40 FPGA is used on the TRBv2. FPGA registers r/w adress bits r 0 31 26 not used ADO_LV 25 0 r 1 31 lvl2 busy 30:lvl1_fifo ...
DescriptionOfTDC
TDC is connected with FPGA thru two interfaces: * JTAG * Parallel JTAG interface It is used for programming status register and control register of TDC's ...
GeneralDescription
How to start 1. Below you can find images for TRB. If you cannot find your image, mail to Radek(rtrebacz #64;gmail.com). Lets include information about NFS server ...
HowToPrepareServerForTrb
This page tries to explain how to prepare server to handle trb version2. assumptions: 1. server has ethernet interface eth0 with IP: 192.168.0.1 1. trb has ...
TDCReadoutBoardV2
TRBv2 How To * TRBv2 HowTo Errors found in previous design versions * Things we learned from ETRAX_FS_DEV1 * Errors in TRBv2A * Errors in TRBv2B * ...
TRBProgressReports
Radek TIPS about DAQ, kernel, etc. manual about DAQ readout scripts TRBvIIHowTo for trb v2 AnaSimMay07 1 Quantum Mechanic very well ...
TRBTigerSHARC
TigerSHARC PIN Number of CMOS PINs Comments PINs connected to Virtex4 SCLKRAT 3 PLL muliplier, can be hardwired to 000 at 125MHz 0 SCLK 1 ...
Number of topics: 8
 
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