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SPIFlashProgramming
SPI controller description The SPI FlashROM controller is attached to RegIO data bus. The user interface consists of two 32bit registers, and one BlockRAM for data ...
TrbNetAddresses
Network Addresses Each network member needs an unique 16Bit address. A network member is not necessarily equal to some piece of hardware: A normal TRB2 board has two ...
TrbNetDatafields
Common definitions for the use of TRBNets datafields Packet types The packet type is sent with each 64 bit packet Name Type Description F1 F2 F3 ...
TrbNetEntities
Overview The "normal" TrbNetEndPoint consists of up to 16 TrbNetIOBUF. Special endpoints for dedicated reasons have only a subset of TrbNetIOBUF in order to keep ressources ...
TrbNetMonitoring
Main.BorislavMilanovic 27 Jul 2009 TRBnet Monitoring System On this page, the new monitoring facility for the TrbNet will be presented. Any user may feel free to ...
TrbNetOnewire
Trb Net Onewire interface This entity provides a very simple 1 wire master to read out the id of a 1 wire device. It does not support busses with more than one device ...
TrbNetUsersGuide
Overview $ trbnet_full_endpoint.pdf : The hades_full_endpoint entity is the central part to connect to the network. Overview Short description of the ports ...
VHDLCodeStyle
Hardware programming guidelines * Synchronous design * synchronization of external signals (at very high frequencies use two register) * never ...
VHDLConstraints
Information on using VHDL Constraints Lattice constraints Constraints for Lattice FPGAs should be located in a separate LPF file, especially if these constraints ...
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