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XilinxPart
(29 May 2006,
MarekPalka
)
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dit
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MarekPalka
- 29 May 2006
Xilinx registers
Address 0x0:
bits
7
6
5
4
3
2
1
0
-
-
-
-
-
-
TDO of jtag port
CY_config_done pin status
TDO of jtag port
Address 0x4:
bits
7
6
5
4
3
2
1
0
Xilinx release, set to 1 for Cypress control
Sharc Reset
-
Reconfig
-
TCK
TMS
TDI
- Write 0x90 to address 0x05200004 of Xilinx for Cypress control.
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Topic revision: r1 - 29 May 2006,
MarekPalka
DaqSlowControl
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