Backlinks to JanMichel in all Webs (Search Main Web only)

Results from Main web retrieved at 18:25 (Local)

HadesDaqSlowControlGroup
HadesDaqSlowControlGroup Please change this topic to add new members in the HadesDaqSlowControlGroup: These are the members of HadesDaqSlowControlGroup: * Set ...
HadesInnerTofGroup
Edit this topic to add a description to the HadesInnerTofGroup
WebStatistics
Apr 2007 629 0 0 117 WebHome 15 HadesSimAnaGroup 14 TorstenHeinz 14 PeterThoeny 13 WebChanges 12 PauloFonte 12 SimonLan...
WikiUsers
List of Foswiki users Below is a list of users with accounts. If you want to edit topics or see protected areas of the site then you can get added to the list by ...
Number of topics: 4

Results from DaqSlowControl web retrieved at 18:25 (Local)

CodeRepositoriesCVS
CVS Basics Here are some most often used CVS commands. After you got your local copy of a module, all the CVS commands related to the module you should do insi...
DAQUpgradeInstallation
DAQ Upgrade Installation of TRB, AddOn, Network... Trigger Distribution * RPC: One PECL LVDS converter on each sector * Shower: Same distributor board a...
DAQUpgradeLogbook
Open Tasks Tasks currently on our agenda: * Remove obsolete cables still a topic ; ) (Everybody who is familiar with the old setup) * Install temperature...
DaqTodoList
Short term To Do List DAQ Documentation Prio. Topic Status Person 5 In depth documentation of CTS settings behaviour not started ...
DaqUpgrade
The Upgrade of the HADES DAQ * DaqUpgradeOverview * DaqNetwork * DaqUpgradeGbE * DaqUpgradeMDCOverview * DaqUpgradeRICHOverview * DAQUpgradeTOFA...
DetectorAndElectronicsConferences
Some electronics, DAQ and Detector related conferences we might want to have some contributions at. Date Description Deadline 23.06.13 27.06.13 Anim...
EtraxTRBInterface
Interface between Etrax and FPGA on TRB ("TrbNet edition") Interface The interface between Etrax and FPGA on the TRB2 uses 2 data ports (Port B and C) of the Etr...
ListOfBoards
List of Boards This should be a complete list of all used boards in the HADES DAQ context. For the running system, such a list is needed to assign the network add...
MDCUpgradeInstallation
Installation and Testing of new MDC DAQ components * OEPBasicTests Testing OEPs and first time programming in Lab * InformationForOEPMounting Bookkeepin...
MDCUpgradeOld
Readout Setup v1 : AddOnv1 and other outdated information Rossendorf Dec07 discussion In Rossendorf we had a discussion about the MDC readout project. The Rossen...
MDCUpgradeWorks2010
MDC Upgrade the final phase Meetings The first meeting of this working period will take place on Monday, 4.1.2010 at 10 a.m. in the upper counting house. Plan...
MdcReadoutupgrademeeting
Weekly meeting on MDC readout upgrade Main.BurkhardKolb 08 Sep 2009 Participants: Main.BurkhardKolb, Main.JanMichel, Main.JoernWuestenfeld, Main.KathrinGoeb...
NetworkAddresses
TRBNet Addresses Here are some suggestions for TrbNet Addresses in the final detector setup. They were choosen based on the following premises: * The addresses...
NewTriggerBusToDo
Not the official milestones, but some pragmatic steps: Simulations VHDL simulation done by Ingo. First important step is to have a running chain with 2 dummy APL...
OEPBasicTests
Initialize new OEPs I. Connect JTAG cable, then power cable I. Check that 1 LED is on I. Program board via JTAG from IspVM. * Program FPGA directly...
OEPNetworkAddresses
Network Addresses of MDC Motherboards/OEPs According to NetworkAddresses, all OEP get TrbNet addresses in the range between 0x2000 to 0x2FFF. The second hex digit...
OutdatedPages
List of outdated pages This entry will service as harbour for all outdated and obsolete topics in the DaqSlowControl Web. Contents Main.JanMichel 12 Dec 2009...
ProposalAndFeaturesTRB3
Layout Proposal (obsolete): * TRB3_layout_proposal1.pdf: Layout proposal * TRB3 updated layout: Key Features * 4 times LFE3 70E(A) 8FN672C for TDC...
TDCReadoutBoardV2cErrors
Add connection between temperature sensor and FPGA (additional to connection to Etrax) (Fix on Trbv2: wire from via next to Pin1 of temperature sensor to JP266 te...
TRBBoardErrors
Errors found in previous design versions * Things we learned from ETRAX_FS_DEV1 * Errors in TRBv2A * Errors in TRBv2B * Errors in TRBv2C * Errors f...
TRBSourceList
Source codes for etrax fs on hadeb05.gsi.de: binary file description ...
TestLogBook
All tables can be edited directly. Use the "Edit table" button underneath each table! Logs for all tests Here are some tables to collect all necessary data for a...
TrbNetAddresses
Network Addresses Each network member needs an unique 16Bit address. A network member is not necessarily equal to some piece of hardware: A normal TRB2 board has ...
TrbNetConfiguration
Network configuration A lot of parameters cn be set using the generics in each top entity. Nevertheless, some of these have to be common for all network devices. ...
TrbNetFiles
TRBNet Files This is a list of files found in the cvs. The optical link is missing at the moment. Low level parts Fifos $ trb_net_fifo: A standard fifo entit...
TrbNetMediaInterfaces
Media Interfaces For every kind of network medium we need an dedicated media interface. For example there is an lvds interface (200MBit), an optical link interfac...
TrbNetOnewire
Trb Net Onewire interface This entity provides a very simple 1 wire master to read out the id of a 1 wire device. It does not support busses with more than one de...
TrbNetRegIO
Reading and Writing registers over the network TrbNetRegIO is a simple interface to read and write registers inside your application from anywhere on the network....
TrbNetStreamingAPI
Trbnet Streaming API A streaming API allows an application to be inserted into the data stream. There it can fullfill two different tasks: It can simply preproces...
TrbPatches
AddOns The pictures shown are a sized down. Download the file from the table to see the high resolution version. Trb2 B Connect Temperature Sensor to FPGA: Via o...
TriggerLvl1Information
LVL1 Trigger Definitions * All information about LVL1 triggers will be sent in a packet using TrbNet and the optical network. * A fast trigger strobe for ...
VHDLCodeInformation
General Information about VHDL Code 1 Recommendations for a common VHDL code style 1 Using VHDL Constraints Main.JanMichel 03 Jul 2007
VHDLConstraints
Information on using VHDL Constraints Lattice constraints Constraints for Lattice FPGAs should be located in a separate LPF file, especially if these constraints...
WebHome
The Hades Data Aquisition and Slow Control System Welcome to the DaqSlowControl web used by .HadesDaqSlowControlGroup. Please use this tool frequently and add/cha...
WebNotify
This is a subscription service to be automatically notified by e mail when topics change in this DaqSlowControl web. This is a convenient service, so you do not h...
WebStatistics
Statistics for DaqSlowControl Web Month: Topic views: Topic saves: File uploads: Most popular topic views: Top contributors for topic save and up...
Number of topics: 36

Results from Sandbox web retrieved at 18:25 (Local)

TestTopicJ
Nothing to see here... Main.JanMichel 03 Jul 2007
WebStatistics
Apr 2007 51 0 0 44 WebHome 4 WebSearch 1 TestTopic3 1 TestTopic4 1 JehadMousaSandbox May 2007 930 0 0 77...
Number of topics: 2
Copyright © by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
Ideas, requests, problems regarding Foswiki Send feedback | Imprint | Privacy Policy (in German)