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HadesDaqSlowControlGroup
HadesDaqSlowControlGroup Please change this topic to add new members in the HadesDaqSlowControlGroup: These are the members of HadesDaqSlowControlGroup: * Set ...
r108 - 2023-07-17 - 10:27 by BehruzKardan
WebStatistics
Apr 2007 629 0 0 117 WebHome 15 HadesSimAnaGroup 14 TorstenHeinz 14 PeterThoeny 13 WebChanges 12 PauloFonte 12 SimonLan...
r415 - 2024-04-20 - 00:00 by AdminUser
WikiUsers
List of Foswiki users Below is a list of users with accounts. If you want to edit topics or see protected areas of the site then you can get added to the list by ...
r1179 - 2024-04-20 - 04:28 by AdminUser
Number of topics: 3

Results from DaqSlowControl web retrieved at 12:21 (Local)

DaqUpgradeRICHOverview
RICH readout structure General description of the system RICH modules Module descriptions APV25S1 information Details on APV25S1 Manual Main.MichaelBoehmer ...
r3 - 2010-04-29 - 10:42 by MichaelBoehmer
DaqUpgradeSubEventAdvancedDebugBlock
Main goal The Advanced Subevent Debug Block (ASDB) is being proposed in strict accordance to the existing HADES subevent header structure. It enhances the feature...
r2 - 2008-10-02 - 12:00 by MichaelBoehmer
RichFEEandDAQUpgrade
First light : ) Despite the fact the the description below is really outdated, I can pronounce the first really important step from connecting the new RICH ADCM t...
r3 - 2008-12-22 - 17:51 by MichaelBoehmer
TrbNetRegIO
Reading and Writing registers over the network TrbNetRegIO is a simple interface to read and write registers inside your application from anywhere on the network....
r18 - 2009-09-11 - 12:24 by JanMichel
TrbNetStreamedEventBuilding
Streamed Event Building The name "streamed event building" comes from the fact that inside the network there is no place where we can guarantee to be able to stor...
r9 - 2009-07-09 - 12:49 by JanMichel
VHDLCodeStyle
Hardware programming guidelines * Synchronous design * synchronization of external signals (at very high frequencies use two register) * never...
r17 - 2009-10-27 - 19:05 by JanMichel
VHDLConstraints
Information on using VHDL Constraints Lattice constraints Constraints for Lattice FPGAs should be located in a separate LPF file, especially if these constraints...
r7 - 2009-02-17 - 12:44 by MichaelBoehmer
ViewLogic
Graphical design system for logic designs. Main.MichaelBoehmer 20 Mar 2007
NEW - 2007-03-20 - 14:53 by MichaelBoehmer
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r12 - 2015-07-06 - 14:34 by BurkhardKolb
Number of topics: 9
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