----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:55:23 07/17/2008 
-- Design Name: 
-- Module Name:    display_ctrl - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

--------entity
entity display_ctrl is
    Port ( CPLD_CLK : in  STD_LOGIC;
	         CHOOSE : in std_logic;
				ENTRY_SAVE_IN : in std_logic_vector(15 downto 0);
				ENTRY_IN : in std_logic_vector(3 downto 0);
            DISP_D_d : out  std_logic_vector(7 downto 0);
            DISP_WR_d : out  std_logic;
            DISP_A_d : out  std_logic_vector(1 downto 0));
end display_ctrl;
--------entity



architecture display_ctrl of display_ctrl is
--  signal diff_in_i : std_logic_vector(7 downto 0);
  signal busy : std_logic := '0';
  signal entry : std_logic_vector(3 downto 0) := "0000";
  
  signal choose_sig : std_logic;
  signal entry_save : std_logic_vector(15 downto 0);
  
  signal part_sig_0 : std_logic_vector(3 downto 0);
  signal part_sig_1 : std_logic_vector(3 downto 0);
  signal part_sig_2 : std_logic_vector(3 downto 0);
  signal part_sig_3 : std_logic_vector(3 downto 0);
  
  signal reset_counter : std_logic := '0';
  signal counter : std_logic_vector(3 downto 0) := "0000";
  signal counter1 : std_logic_vector(7 downto 0) := x"00";
  signal test_counter : std_logic_vector(3 downto 0) := "0000";
  signal address_counter : std_logic_vector(1 downto 0) := "00";
  signal address_counter_enable : std_logic := '0';
  signal reset_address_counter : std_logic := '0';
  signal disp_counter: std_logic_vector(24 downto 0) := "0000000000000000000000000";
  signal reset_disp_counter : std_logic := '0';
  
  signal reset_state_n : std_logic := '0';
  
  signal position0 : std_logic_vector(7 downto 0) := "00000000";
  signal position1 : std_logic_vector(7 downto 0) := "00000000";
  signal position2 : std_logic_vector(7 downto 0) := "00000000";
  signal position3 : std_logic_vector(7 downto 0) := "00000000";
  signal position4 : std_logic_vector(7 downto 0) := "00000000";
  signal position5 : std_logic_vector(7 downto 0) := "00000000";
  signal position6 : std_logic_vector(7 downto 0) := "00000000";
  signal position7 : std_logic_vector(7 downto 0) := "00000000";
  signal position8 : std_logic_vector(7 downto 0) := "00000000";
  
  signal stelle0 : std_logic_vector(7 downto 0) := "00000000";
  signal stelle1 : std_logic_vector(7 downto 0) := "00000000";
  signal stelle2 : std_logic_vector(7 downto 0) := "00000000";
  signal stelle3 : std_logic_vector(7 downto 0) := "00000000";
  
  signal buf_DISP_D : std_logic_vector(7 downto 0):= "00000000";
  signal buf_DISP_A : std_logic_vector(1 downto 0):= "00";
  signal buf_DISP_WR : std_logic:= '0';
  signal next_DISP_D : std_logic_vector(7 downto 0):= "00000000";
  signal next_DISP_A : std_logic_vector(1 downto 0):= "00";
  signal next_DISP_WR : std_logic:= '0';
  
  signal entry_sig : std_logic_vector(15 downto 0);
  
  signal disp_move: std_logic := '0';
  type state_type is (ADDRESS, DATA, WRIT, HOLD);
  signal next_state, current_state: state_type;
  type state_disp_type is (DISP0, DISP1, DISP2, DISP3, DISP4, DISP5, DISP6, DISP7, 
                            DISP8, DISP9, DISP10, DISP11, DISP12);
  signal next_disp_state, current_disp_state: state_disp_type;


begin	
	
process (CPLD_CLK, reset_state_n)
begin  
  if rising_edge(CPLD_CLK) then
	 if reset_state_n = '0' then
       current_state <= ADDRESS;
	 else
	    current_state <= next_state;
    end if;
  end if;
end process;

process (CPLD_CLK)
begin  
  if rising_edge(CPLD_CLK) then
     if reset_state_n = '0' then
         current_disp_state <= DiSP0;
	  else
         current_disp_state <= next_disp_state;
	  end if;
  end if;
end process;

process (CPLD_CLK)
begin  
if rising_edge(CPLD_CLK) then
       if counter = x"4" then
		     counter <= counter;
			  reset_state_n <= '1';
		 else
		     counter <= counter +1; 
           reset_state_n <= '0';
   	 end if;
end if;
end process;

process (CPLD_CLK, reset_state_n)
begin  
if rising_edge(CPLD_CLK) then
   if reset_counter = '1' then
     counter1 <= (others => '0');
   else
     counter1 <= counter1 + 1;
  end if;  
end if;
end process;

process (CPLD_CLK)
begin  
if rising_edge(CPLD_CLK) then
   if reset_disp_counter = '1' then
     disp_counter <= (others => '0');
   else
     disp_counter <= disp_counter + 1;
  end if;  
end if;
end process;

process (CPLD_CLK)
begin  
if rising_edge(CPLD_CLK) then
   if reset_address_counter = '1' then
       address_counter <= (others => '0');
   elsif address_counter_enable ='1' then
      address_counter <= address_counter +1;
  end if;  
end if;
end process;

entry <= ENTRY_IN;
entry_sig <= ENTRY_SAVE_IN;
choose_sig <= CHOOSE;

process(CPLD_CLK, choose_sig)
begin
if choose_sig = '0' then
  if rising_edge(CPLD_CLK) then
	     entry_save <= entry_sig;
  end if;
end if;
end process;

process (entry, stelle0, stelle1, stelle2, stelle3, position0, 
          position1, position2, position3, position4, position5, 
          position6, position7, position8, disp_move)
begin


if choose_sig = '1' then
-- default value
--LED_ERROR <=  '1';
--LED_GOOD  <=  '1';
--LED_CNT_1 <=  '1';
--LED_CNT_2 <=  '1';
position4 <= "00000000";

if entry = 0 then
position0<=CONV_STD_LOGIC_VECTOR(character'pos('B'),8);
position1<=CONV_STD_LOGIC_VECTOR(character'pos('U'),8);
position2<=CONV_STD_LOGIC_VECTOR(character'pos('S'),8);
position3<=CONV_STD_LOGIC_VECTOR(character'pos('Y'),8);
elsif entry = 1 then
position0<=CONV_STD_LOGIC_VECTOR(character'pos('L'),8);
position1<=CONV_STD_LOGIC_VECTOR(character'pos('V'),8);
position2<=CONV_STD_LOGIC_VECTOR(character'pos('L'),8);
position3<=CONV_STD_LOGIC_VECTOR(character'pos('1'),8);
elsif entry = 10 then
position0<=CONV_STD_LOGIC_VECTOR(character'pos('L'),8);
position1<=CONV_STD_LOGIC_VECTOR(character'pos('V'),8);
position2<=CONV_STD_LOGIC_VECTOR(character'pos('L'),8);
position3<=CONV_STD_LOGIC_VECTOR(character'pos('2'),8);
elsif entry = 11 then
position0<=CONV_STD_LOGIC_VECTOR(character'pos('E'),8);
position1<=CONV_STD_LOGIC_VECTOR(character'pos('R'),8);
position2<=CONV_STD_LOGIC_VECTOR(character'pos('R'),8);
position3<=CONV_STD_LOGIC_VECTOR(character'pos('O'),8);
position4<=CONV_STD_LOGIC_VECTOR(character'pos('R'),8);
--LED_ERROR <= '0';
elsif entry = 100 then
position0<=CONV_STD_LOGIC_VECTOR(character'pos('C'),8);
position1<=CONV_STD_LOGIC_VECTOR(character'pos('A'),8);
position2<=CONV_STD_LOGIC_VECTOR(character'pos('L'),8);
position3<=CONV_STD_LOGIC_VECTOR(character'pos('I'),8);
position4<=CONV_STD_LOGIC_VECTOR(character'pos('B'),8);
position5<=CONV_STD_LOGIC_VECTOR(character'pos('R'),8);
position6<=CONV_STD_LOGIC_VECTOR(character'pos('A'),8);
position7<=CONV_STD_LOGIC_VECTOR(character'pos('T'),8);
position8<=CONV_STD_LOGIC_VECTOR(character'pos('E'),8);

--elsif entry = 0101 then
--elsif entry = 0110 then
--elsif entry = 0111 then
--elsif entry = 1000 then
--elsif entry = 1001 then
--elsif entry = 1010 then
--elsif entry = 1011 then
--elsif entry = 1100 then
--elsif entry = 1101 then
--elsif entry = 1110 then
--elsif entry = 1111 then

end if;

if position4 = 0 then
	disp_move <= '1';
else
   disp_move <= '0';
end if;

else

part_sig_0 <= entry_save(3 downto 0);
part_sig_1 <= entry_save(7 downto 4);
part_sig_2 <= entry_save(11 downto 8);
part_sig_3 <= entry_save(15 downto 12);


disp_move <= '0';
case part_sig_3 is

when  "0000" => position0 <= "00110000";
when  "0001" => position0 <= "00110001";
when  "0010" => position0 <= "00110010";
when  "0011" => position0 <= "00110011";
when  "0100" => position0 <= "00110100";
when  "0101" => position0 <= "00110101";
when  "0110" => position0 <= "00110110";
when  "0111" => position0 <= "00110111";
when  "1000" => position0 <= "00101000";
when  "1001" => position0 <= "00111001";
when  "1010" => position0 <= "01000001";
when  "1011" => position0 <= "01000010";
when  "1100" => position0 <= "01000011";
when  "1101" => position0 <= "01000100";
when  "1110" => position0 <= "01000101";
when  "1111" => position0 <= "01000110";
when others  => position0 <= "01000110";
	
end case;
case part_sig_2 is

when  "0000" => position1 <= "00110000";
when  "0001" => position1 <= "00110001";
when  "0010" => position1 <= "00110010";
when  "0011" => position1 <= "00110011";
when  "0100" => position1 <= "00110100";
when  "0101" => position1 <= "00110101";
when  "0110" => position1 <= "00110110";
when  "0111" => position1 <= "00110111";
when  "1000" => position1 <= "00111000";
when  "1001" => position1 <= "00111001";
when  "1010" => position1 <= "01000001";
when  "1011" => position1 <= "01000010";
when  "1100" => position1 <= "01000011";
when  "1101" => position1 <= "01000100";
when  "1110" => position1 <= "01000101";
when  "1111" => position1 <= "01000110";
when others  => position1 <= "01000110";

	
end case;
case part_sig_1 is

when  "0000" => position2 <= "00110000";
when  "0001" => position2 <= "00110001";
when  "0010" => position2 <= "00110010";
when  "0011" => position2 <= "00110011";
when  "0100" => position2 <= "00110100";
when  "0101" => position2 <= "00110101";
when  "0110" => position2 <= "00110110";
when  "0111" => position2 <= "00110111";
when  "1000" => position2 <= "00111000";
when  "1001" => position2 <= "00111001";
when  "1010" => position2 <= "01000001";
when  "1011" => position2 <= "01000010";
when  "1100" => position2 <= "01000011";
when  "1101" => position2 <= "01000100";
when  "1110" => position2 <= "01000101";
when  "1111" => position2 <= "01000110";
when others  => position2 <= "01000110";

end case;
case part_sig_0 is

when  "0000" => position3 <= "00110000";
when  "0001" => position3 <= "00110001";
when  "0010" => position3 <= "00110010";
when  "0011" => position3 <= "00110011";
when  "0100" => position3 <= "00110100";
when  "0101" => position3 <= "00110101";
when  "0110" => position3 <= "00110110";
when  "0111" => position3 <= "00110111";
when  "1000" => position3 <= "00111000";
when  "1001" => position3 <= "00111001";
when  "1010" => position3 <= "01000001";
when  "1011" => position3 <= "01000010";
when  "1100" => position3 <= "01000011";
when  "1101" => position3 <= "01000100";
when  "1110" => position3 <= "01000101";
when  "1111" => position3 <= "01000110";
when others  => position3 <= "01000110";

end case;

end if;

end process;
	
comb_logic : process(current_disp_state, disp_counter, stelle0, stelle1, stelle2, 
                      stelle3, position0, position1, position2, position3, position4, position5, 
                      position6, position7, position8, disp_move)
begin

if disp_move = '1' then
   case current_disp_state is
      when DISP0 =>
		reset_disp_counter <= '0';
	   stelle0 <= position0;
		stelle1 <= position1;
	   stelle2 <= position2;
	   stelle3 <= position3;
		if disp_counter = x"1fffc18" then
		  next_disp_state <= DISP1;
		  reset_disp_counter <= '1';
		else
		  next_disp_state <= DISP0;
		end if;
      when DISP1 =>
		reset_disp_counter <= '0';
		stelle0 <= position1;
		stelle1 <= position2;
	   stelle2 <= position3;
	   stelle3 <= position4;
		if disp_counter= x"1fffc18" then
		  next_disp_state <= DISP2;
		  reset_disp_counter <= '1';
		else
		  next_disp_state <= DISP1;
		end if;
		when DISP2 =>
		reset_disp_counter <= '0';
		stelle0 <= position2;
		stelle1 <= position3;
	   stelle2 <= position4;
	   stelle3 <= position5;
		if disp_counter= x"1fffc18" then
		  next_disp_state <= DISP3;
		  reset_disp_counter <= '1';
		else
		  next_disp_state <= DISP2;
		end if;
		when DISP3 =>
		reset_disp_counter <= '0';
		stelle0 <= position3;
		stelle1 <= position4;
	   stelle2 <= position5;
	   stelle3 <= position6;
		if disp_counter= x"1fffc18" then
		  next_disp_state <= DISP4;
		  reset_disp_counter <= '1';
		else
		  next_disp_state <= DISP3;
		end if;
		when DISP4 =>
		reset_disp_counter <= '0';
		stelle0 <= position4;
		stelle1 <= position5;
	   stelle2 <= position6;
	   stelle3 <= position7;
		if disp_counter= x"1fffc18" then
		  next_disp_state <= DISP5;
		  reset_disp_counter <= '1';
		else
		  next_disp_state <= DISP4;
		end if;
		when DISP5 =>
		reset_disp_counter <= '0';
		stelle0 <= position5;
		stelle1 <= position6;
	   stelle2 <= position7;
	   stelle3 <= position8;
		if disp_counter= x"1fffc18" then
		  next_disp_state <= DISP6;
		  reset_disp_counter <= '1';
		else
		  next_disp_state <= DISP5;
		end if;
		when DISP6 =>
		reset_disp_counter <= '0';
		stelle0 <= position6;
		stelle1 <= position7;
	   stelle2 <= position8;
	   stelle3 <= "00100000";
		if disp_counter= x"1fffc18" then
		  next_disp_state <= DISP7;
		  reset_disp_counter <= '1';
		else
		  next_disp_state <= DISP6;
		end if;
		when DISP7 =>
		reset_disp_counter <= '0';
		stelle0 <= position7;
		stelle1 <= position8;
	   stelle2 <= "00100000";
	   stelle3 <= "00100000";
		if disp_counter= x"1fffc18" then
		  next_disp_state <= DISP8;
		  reset_disp_counter <= '1';
		else
		  next_disp_state <= DISP7;
		end if;
		when DISP8 =>
		reset_disp_counter <= '0';
		stelle0 <= position8;
		stelle1 <= "00100000";
	   stelle2 <= "00100000";
	   stelle3 <= "00100000";
		if disp_counter= x"1fffc18" then
		  next_disp_state <= DISP9;
		  reset_disp_counter <= '1';
		else
		  next_disp_state <= DISP8;
		end if;
		when DISP9 =>
		reset_disp_counter <= '0';
		stelle0 <= "00100000";
		stelle1 <= "00100000";
	   stelle2 <= "00100000";
	   stelle3 <= "00100000";
		if disp_counter= x"1fffc18" then
		  next_disp_state <= DISP10;
		  reset_disp_counter <= '1';
		else
		  next_disp_state <= DISP9;
		end if;
		when DISP10 =>
		reset_disp_counter <= '0';
		stelle0 <= "00100000";
		stelle1 <= "00100000";
	   stelle2 <= "00100000";
	   stelle3 <= position0;
		if disp_counter= x"1fffc18" then
		  next_disp_state <= DISP11;
		  reset_disp_counter <= '1';
		else
		  next_disp_state <= DISP10;
		end if;
		when DISP11 =>
		reset_disp_counter <= '0';
		stelle0 <= "00100000";
		stelle1 <= "00100000";
	   stelle2 <= position0;
	   stelle3 <= position1;
		if disp_counter= x"1fffc18" then
		  next_disp_state <= DISP12;
		  reset_disp_counter <= '1';
		else
		  next_disp_state <= DISP11;
		end if;
		when DISP12 =>
		reset_disp_counter <= '0';
		stelle0 <= "00100000";
		stelle1 <= position0;
	   stelle2 <= position1;
	   stelle3 <= position2;
		if disp_counter= x"1fffc18" then
		  next_disp_state <= DISP0;
		  reset_disp_counter <= '1';
		else
		  next_disp_state <= DISP12;
		end if;

end case;
else
      stelle0 <= position0;
	   stelle1 <= position1;
	   stelle2 <= position2;
	   stelle3 <= position3;
end if;
  
end process;

disp_write : process(current_state, counter1, address_counter, address_counter_enable, 
                      next_state, reset_counter, buf_DISP_A, buf_DISP_WR, buf_DISP_A,buf_DISP_D, stelle3, 
                      stelle2, stelle1, stelle0)
begin	

	--defalut values
	reset_counter <= '0';
	address_counter_enable <= '0';
	reset_address_counter <= '0';
--	next_DISP_D <= buf_DISP_D;
--	next_DISP_A <= buf_DISP_A;
--	next_DISP_WR <= buf_DISP_WR;

	
	
case current_state is
		  
		 when ADDRESS    =>
		   address_counter_enable <= '0';
			next_DISP_A <= address_counter;
			next_DISP_WR <= '1';
			if counter1 = x"10" then
				next_state <= DATA;
				reset_counter <= '1';
			else
				next_state <= ADDRESS;
			end if;
	
		 when DATA       =>
		 address_counter_enable <= '0';
		 next_DISP_A <= address_counter;
		 reset_counter <= '0';
		 next_DISP_WR <= '0';
		 if address_counter = "00" then
			  next_DISP_D <= stelle3;
			  elsif  address_counter = "01" then
			  next_DISP_D <= stelle2;
			  elsif  address_counter = "10" then
			  next_DISP_D <= stelle1;
			  elsif  address_counter = "11" then
			  next_DISP_D <=	stelle0;
		 end if;
		 if counter1 = x"20" then
			next_state <= WRIT;
			reset_counter <= '1';
		 else
			next_state <= DATA;
		 end if;
		
		  when WRIT =>
		  address_counter_enable <= '0';

			next_DISP_WR <= '0';
			reset_counter <= '0';
			if counter1 = x"14" then
			next_state <= HOLD;
			reset_counter <= '1';
			else
			next_state <= WRIT;
			end if;
	
	
		 when HOLD    =>

			next_DISP_WR <= '1';
			if counter1 = x"6" then
				next_state <= ADDRESS;
				reset_counter <= '1';
				address_counter_enable <= '1';
			else
				next_state <= HOLD;
			end if;
		
		end case;

end process;


process (CPLD_CLK)
begin  
if rising_edge(CPLD_CLK) then
  if reset_state_n = '0' then
     buf_DISP_D <="00000000";
	  buf_DISP_A <="00";
	  buf_DISP_WR <='0';
  else
     buf_DISP_D <= next_DISP_D;
	  buf_DISP_A <= next_DISP_A;
	  buf_DISP_WR <= next_DISP_WR;
	
  end if;
end if;

end process;

DISP_D_d <= buf_DISP_D;
DISP_A_d <= buf_DISP_A;
DISP_WR_d <= buf_DISP_WR;

end display_ctrl;