library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; -- use work.support.all; library UNISIM; use UNISIM.VCOMPONENTS.all; entity gp_add_on is port( -- -- # NET +<3> LOC = E8; -- ADDON_RESET :in std_logic; ADO_TTL : inout std_logic_vector(34 downto 0); ADO_TTL_OUT : out std_logic_vector(3 downto 0); -- ------------------------------------------------------------------------------ -- -- LVL1 -- ------------------------------------------------------------------------------ B_R : in std_logic; B_RB : out std_logic; B_RD : in std_logic_vector(3 downto 0); B_RE : out std_logic; B_RS : in std_logic; ------------------------------------------------------------------------------ -- LVL2 ------------------------------------------------------------------------------ B_T : in std_logic; B_TB : out std_logic; B_TB_B2_DIR :out std_logic; B_TB_B1_DIR :out std_logic; B_TB_D_DIR :out std_logic; B_TB_E2_DIR :out std_logic; B_TB_E1_DIR :out std_logic; B_TD :in std_logic_vector(3 downto 0); B_TE : out std_logic; B_TS : in std_logic; ------------------------------------------------------------------------------- -- to next trb dtu data ------------------------------------------------------------------------------- ------------------------------------------------------------------------------ -- LVL1 -------------------------------------------------------------------------------- A_R : out std_logic; A_RB : in std_logic; A_RD : out std_logic_vector(3 downto 0); A_RE : in std_logic; A_RS : out std_logic; ------------------------------------------------------------------------------ -- LVL2 ------------------------------------------------------------------------------ A_T : out std_logic; A_TB : in std_logic; A_TB_B2_DIR :out std_logic; A_TB_B1_DIR :out std_logic; A_TB_D_DIR :out std_logic; A_TB_E2_DIR :out std_logic; A_TB_E1_DIR :out std_logic; A_TD : out std_logic_vector(3 downto 0); A_TE : in std_logic; A_TS : out std_logic; CPLD_CLK : in std_logic; -- DIFF_IN : in std_logic_vector(7 downto 0); DISP_A : out std_logic_vector(1 downto 0); DISP_D : out std_logic_vector(7 downto 0); DISP_WR : out std_logic; -- -- DISP_A<0> LOC = M2; -- -- DISP_A<1> LOC = L5; -- -- DISP_D<0> LOC = M3; -- -- DISP_D<1> LOC = M4; -- -- DISP_D<2> LOC = N2; -- -- DISP_D<3> LOC = N3; -- -- DISP_D<4> LOC = P1; -- -- DISP_D<5> LOC = R1; -- -- DISP_D<6> LOC = T1; -- -- DISP_WR LOC = L2; -- -- FROM_LVDS<28> LOC = C16; -- -- FROM_LVDS<29> LOC = D16; -- -- FROM_LVDS<30> LOC = E14; -- -- FS_PE<0> LOC = A7; -- -- FS_PE<1> LOC = K1; -- -- FS_PE<2> LOC = J13; -- -- FS_PE<4> LOC = C10; -- -- FS_PE<5> LOC = N8; -- -- FS_PE<6> LOC = P6; -- -- FS_PE<7> LOC = P7; -- -- FS_PE<8> LOC = P8; -- -- FS_PE<9> LOC = P9; -- -- FS_PE<10> LOC = R7; -- -- FS_PE<11> LOC = R8; -- -- FS_PE<12> LOC = T7; -- -- FS_PE<13> LOC = T8; -- -- FS_PE<14> LOC = T9; -- -- FS_PE<15> LOC = M7; -- -- FS_PE<16> LOC = N6; -- -- FS_PE<17> LOC = N7; -- -- GND LOC = L11; LED_CNT_1 :out std_logic; LED_CNT_2 :out std_logic; -- -- LED_CTU_EN :out std_logic; LED_ERROR :out std_logic; LED_GOOD :out std_logic -- -- LED_LVDS_EN :out std_logic ); end gp_add_on; architecture gp_add_on of gp_add_on is component display_ctrl is port( CPLD_CLK : in std_logic; CHOOSE : in std_logic; ENTRY_SAVE_IN : in std_logic_vector(15 downto 0); ENTRY_IN : in std_logic_vector(3 downto 0); DISP_A_d : out std_logic_vector(1 downto 0); DISP_D_d : out std_logic_vector(7 downto 0); DISP_WR_d : out std_logic ); end component display_ctrl; component event_counter is port( CPLD_CLK : in std_logic; ENABLE_COUNTER_IN : in std_logic; ENTRY_SAVE_OUT : out std_logic_vector(15 downto 0); RESET_COUNTER_IN : in std_logic ); end component event_counter; -- signal buf_DISP_D : std_logic_vector(7 downto 0):= "00000000"; -- signal buf_DISP_A : std_logic_vector(1 downto 0):= "00"; -- signal buf_DISP_WR : std_logic:= '0'; signal sig_choose : std_logic; signal sig_entry_save : std_logic_vector(15 downto 0); signal sig_entry : std_logic_vector(3 downto 0); signal counter : std_logic_vector(15 downto 0); signal enable_counter : std_logic; signal reset_counter : std_logic; begin U1: display_ctrl port map ( CPLD_CLK => CPLD_CLK, CHOOSE => sig_choose, ENTRY_SAVE_IN => sig_entry_save, ENTRY_IN => sig_entry, DISP_A_d => DISP_A, DISP_D_d => DISP_D, DISP_WR_d => DISP_WR ); G1: event_counter port map ( CPLD_CLK => CPLD_CLK, ENABLE_COUNTER_IN => enable_counter, RESET_COUNTER_IN => reset_counter, ENTRY_SAVE_OUT => sig_entry_save ); sig_choose <= '0'; sig_entry <= "0001"; enable_counter <= '1'; end architecture gp_add_on;