#JTAG instructions-Setup registe test_sielect[3:0]=b1110 #Selection of testoutput signal (for testing) enable_error_mark[4]=b1 #Mark events witherror if global error signal set enable_error_bypass[5]=b0 #Bypass TDC chip if global error signal set enable_error[16:6]=b11111111111 #Enable of internal error types for generation of global error signal readout_single_cycle_speed[19:17]=b000 #Serial transmission speed in single cycle mode serial_delay[23:20]=b0000 #Programmable delay of serial input Time unit ~ 1ns serial_delay[25:24]=b00 #Selection of serial strobe type readout_speed_select[26]=b0 #Selection of serial read-out speed token_delay[30:27]=b0000 #Programmable delay of token input Time unit ~ 1ns enable_local_trailer[31]=b0 #Enable of local trailers in read-out enable_local_header[32]=b0 #Enable of local headers in read-out enable_global_trailer[33]=b0 #Enable of global trailers in read-out (only valid for master TDC) enable_global_header[34]=b0 #Enable of global headers in read-out (only valid for master TDC) keep_token[35]=b1 #Keep token until end of event or no more data otherwise pass token after each word read.Must be enabled when using trigger matching. master[36]=b0 #Master chip in token ring enable_bytewise[37]=b0 #Enable of byte-wise readout enable_serial[38]=b0 #Enable of serial read-out (otherwise parallel read-out) enable_jtag_readout[39]=b0 #Enable of readout via JTAG (overrides other readout modes) tdc_id[43:40]=b0100 #TDC identifier in readout select_bypass_inputs[44]=b0 #Select serial in and token in from bypass inputs readout_fifo_size[47:45]=b111 #Effective size of readout fifo reject_count_offset[59:48]=b011111110001 #Reject counter offset defines reject latency together with coarse count offset search_window[71:60]=b000000101101 #Search window in number of clock cycles match_window[83:72]=b000000101100 #Matching window in number of clock cycles leading_resolution[86:84]=b000 #Resolution of leading/trailing edge used to select bits read out. fixed_pattern[114:87]=b0000000000000000000000000000 #Fixed readout pattern (for debugging) enable_fixed_pattern[115]=b0 #Enable readout of fixed pattern (for debugging) max_event_size[119:116]=b1001 #Maximum number of hits per event only valid when using trigger matching reject_readout_fifo_full[120]=b1 #Reject hits when read-out fifo full.otherwise back propagate to L1 buffers enable_readout_occupancy[121]=b0 #Enable readout of buffer occupancies for each event (debugging).Only allowed when using trigger matching. enable_readout_separator[122]=b0 #Enable read-out of separators (debugging)only valid if generation of separators enabled enable_overflow_detect[123]=b1 #Enable overflow detect of L1 buffers (should always be enabled) enable_relative[124]=b0 #Enable read-out of relative time to trigger time tag only valid when using trigger matching enable_relative[125]=b1 #Enable of automatic rejection (should always be enabled if trigger matching) event_count_offset[137:126]=b000000000000 #Event number offset trigger_count_offset[149:138]=b111111110101 #Trigger time tag counter offset used to set effective trigger latency enable_set_counters_on_bunch_reset[150]=b1 #Enable all counters to be set on bunch count reset enable_master_reset_code[151]=b0 #Enable master reset code on encoded_control enable_master_reset_on_event_reset[152]=b0 #Enable master reset of whole TDC on event reset enable_reset_channel_buffer_when_separator[153]=b0 #Enable reset channel buffers when separator enable_separator_on_event_reset[154]=b0 #Enable generation of separator on event reset enable_separator_on_bunch_reset[155]=b0 #Enable generation of separator on bunch reset enable_direct_event_reset[156]=b1 #Enable of direct event reset input pin otherwise taken from encoded control enable_direct_bunch_reset[157]=b1 #Enable of direct bunch reset input pin otherwise taken from encoded control enable_direct_trigger[158]=b1 #Enable of direct trigger input pin otherwise taken from encoded control offset31[167:159]=b000000000 #Offset adjust for channel 31 offset30[176:168]=b000000000 #Offset adjust for channel 30 offset29[185:177]=b000000000 #Offset adjust for channel 29 offset28[194:186]=b000000000 #Offset adjust for channel 28 offset27[203:195]=b000000000 #Offset adjust for channel 27 offset26[212:204]=b000000000 #Offset adjust for channel 26 offset25[221:213]=b000000000 #Offset adjust for channel 25 offset24[230:222]=b000000000 #Offset adjust for channel 24 offset23[239:231]=b000000000 #Offset adjust for channel 23 offset22[248:240]=b000000000 #Offset adjust for channel 22 offset21[257:249]=b000000000 #Offset adjust for channel 21 offset20[266:258]=b000000000 #Offset adjust for channel 20 offset19[275:267]=b000000000 #Offset adjust for channel 19 offset18[284:276]=b000000000 #Offset adjust for channel 18 offset17[293:285]=b000000000 #Offset adjust for channel 17 offset16[302:294]=b000000000 #Offset adjust for channel 16 offset15[311:303]=b000000000 #Offset adjust for channel 15 offset14[320:312]=b000000000 #Offset adjust for channel 14 offset13[329:321]=b000000000 #Offset adjust for channel 13 offset12[338:330]=b000000000 #Offset adjust for channel 12 offset11[347:339]=b000000000 #Offset adjust for channel 11 offset10[356:348]=b000000000 #Offset adjust for channel 10 offset9[365:357]=b000000000 #Offset adjust for channel 9 offset8[374:366]=b000000000 #Offset adjust for channel 8 offset7[383:375]=b000000000 #Offset adjust for channel 7 offset6[392:384]=b000000000 #Offset adjust for channel 6 offset5[401:393]=b000000000 #Offset adjust for channel 5 offset4[410:402]=b000000000 #Offset adjust for channel 4 offset3[419:411]=b000000000 #Offset adjust for channel 3 offset2[428:420]=b000000000 #Offset adjust for channel 2 offset1[437:429]=b000000000 #Offset adjust for channel 1 offset0[446:438]=b000000000 #Offset adjust for channel 0 coarse_count_offset[458:447]=b000000000000 #Offset for coarse time counter dll_tap_adjust[470:459]=b000000000000 #Adjustment of DLL taps -tap 0,1,2,3 dll_tap_adjust[482:471]=b000000000000 #Adjustment of DLL taps -tap 4,5,6,7,8 dll_tap_adjust[494:483]=b000000000000 #Adjustment of DLL taps -tap 8,9,10,11 dll_tap_adjust[506:495]=b000000000000 #Adjustment of DLL taps -tap 12,13,14,15 dll_tap_adjust[518:507]=b000000000000 #Adjustment of DLL taps -tap 16,17,18,19 dll_tap_adjust[530:519]=b000000000000 #Adjustment of DLL taps -tap 20,21,22,22 dll_tap_adjust[542:531]=b000000000000 #Adjustment of DLL taps -tap 24,25,26,27 dll_tap_adjust[554:543]=b000000000000 #Adjustment of DLL taps -tap 28,29,30,31 rc_adjust[566:555]=b000000000000 #Adjustment of R-C delay line.only needed in very high resolution RC mode not_used[569:567]=b000 #not used (rc_adjust 14:12) low_power_mode[570]=b1 #low_power_mode Low power mode of channel buffers width_select[574:571]=b0000 #Pulse width resolution when paired measurements vernier_offset[579:575]=b00000 #Offset in vernier decoding fixed value = 00000 dll_control[583:580]=b0001 #Control of dll (update) DLL charge pump levels (0001) dead_time[585:584]=b00 #Channel dead time between hits test_invert[586]=b0 #Automatic inversion of test pattern only used during production testing test_mode[587]=b0 #Test mode where hit data taken from coretest. Only used during production testing enable_trailing[588]=b1 #Enable of trailing edges enable_leading[589]=b0 #Enable of leading edges mode_rc_compression[590]=b0 #Perform RC interpolation on-chip. Only valid in very high resolution mode mode_rc[591]=b0 #Enable of R-C delay line mode (very high res. mode)only channel 0,4,8,12,16,20,24,28 active dll_mode[593:592]=b00 #Selection of DLL speed mode (update) pll_control[601:594]=b00000100 #Control of PLL (update) serial_clock_delay[605:602]=b0000 #Delay of internal serial clock (update) io_clock_delay[609:606]=b0000 #Delay of internal io clock (update) core_clock_delay[613:610]=b0000 #Delay of internal core clock (update) dll_clock_delay[617:614]=b0000 #Delay of internal dll clock (update) serial_clock_source[619:618]=b00 #Selection of source for serial clock (update) io_clock_source[621:620]=b00 #Selection of clock source for IO signals (update) core_clock_source[623:622]=b00 #Selection of clock source for internal logic dll_clock_source[626:624]=b001 #Selection of clock source for DLL roll_over[638:627]=b111111111111 #Counter roll over value. enable_matching[639]=b1 #Enable of trigger matching enable_pair[640]=b0 #Enable pairing of leading and trailing edges (overrides individual enable of leading/trailing edges)not allowed in very high resolution RC mode enable_ttl_serial[641]=b0 #Enable LV TTL input on:serial_in,serial_bypass_in,token_in,token_bypass_in enable_ttl_control[642]=b0 #Enable LV TTL input on:trigger,bunch_reset,event_reset,encoded_control enable_ttl_reset[643]=b0 #Enable LV TTL input on: reset enable_ttl_clock[644]=b1 #Enable LV TTL inputs on: clk,aux_clock enable_ttl_hit[645]=b0 #Enable LV TTL input on: hit[31:0] setup_parity[646]=b0 #Parity of setup data (even parity)-set by programm #END OF DATA