Design Overview for top_level

PropertyValue
Project Name:d:\ise_demo71\testbench_featuresv2
Target Device:xc3s50
Constraints File:Constraints.ucf
Report Generated:Sunday 04/03/05 at 12:58
Printable Summary (View as HTML)top_level_summary.html

Device Utilization Summary (estimated values)

Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slices:67680% 
Number of Slice Flip Flops:1015360% 
Number of 4 input LUTs:1015360% 
Number of bonded IOBs:2312418% 
Number of GCLKs:1812% 

Performance Summary

PropertyValue
Data Not Yet Available  

Failing Constraints

Constraint(s)RequestedActualLogic Levels
Data Not Yet Available   

Detailed Reports

Report NameStatusLast Date Modified
Synthesis ReportCurrentSunday 04/03/05 at 12:58
Translation ReportOut-of-DateSunday 04/03/05 at 12:45
Map ReportOut-of-DateSunday 04/03/05 at 12:45
Pad ReportOut-of-DateSunday 04/03/05 at 12:45
Place and Route ReportOut-of-DateSunday 04/03/05 at 12:45
Post Place and Route Static Timing ReportOut-of-DateSunday 04/03/05 at 12:45