Design Overview for top_level

PropertyValue
Project Name:d:\ise_demo71\testbench_featuresv2
Target Device:xc3s50
Constraints File:Constraints.ucf
Report Generated:Tuesday 03/29/05 at 08:19
Printable Summary (View as HTML)top_level_summary.html

Device Utilization Summary

Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops:81,5361% 
Number of 4 input LUTs:91,5361% 
Logic Distribution:    
Number of occupied Slices:67681% 
Number of Slices containing only related logic:66100% 
Number of Slices containing unrelated logic:060% 
Total Number 4 input LUTs:101,5361% 
Number used as logic:9   
Number used as a route-thru:1   
Number of bonded IOBs:2312418% 
Number of GCLKs:1812% 

Performance Summary

PropertyValue
Final Timing Score:0
Number of Unrouted Signals:All signals are completely routed.
Number of Failing Constraints:0

Failing Constraints

Constraint(s)RequestedActualLogic Levels
All Constraints Met   

Detailed Reports

Report NameStatusLast Date Modified
Synthesis ReportCurrentSunday 03/27/05 at 12:24
Translation ReportCurrentSunday 03/27/05 at 12:24
Map ReportCurrentTuesday 03/29/05 at 08:18
Pad ReportCurrentTuesday 03/29/05 at 08:19
Place and Route ReportCurrentTuesday 03/29/05 at 08:19
Post Place and Route Static Timing ReportCurrentTuesday 03/29/05 at 08:19