Property | Value |
Project Name: | d:\ise_demo71\testbench_featuresv2 |
Target Device: | xc3s50 |
Constraints File: | Constraints.ucf |
Report Generated: | Tuesday 03/29/05 at 08:19 |
Printable Summary (View as HTML) | top_level_summary.html |
Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Flip Flops: | 8 | 1,536 | 1% | |
Number of 4 input LUTs: | 9 | 1,536 | 1% | |
Logic Distribution: | ||||
Number of occupied Slices: | 6 | 768 | 1% | |
Number of Slices containing only related logic: | 6 | 6 | 100% | |
Number of Slices containing unrelated logic: | 0 | 6 | 0% | |
Total Number 4 input LUTs: | 10 | 1,536 | 1% | |
Number used as logic: | 9 | |||
Number used as a route-thru: | 1 | |||
Number of bonded IOBs: | 23 | 124 | 18% | |
Number of GCLKs: | 1 | 8 | 12% |
Property | Value |
Final Timing Score: | 0 |
Number of Unrouted Signals: | All signals are completely routed. |
Number of Failing Constraints: | 0 |
Constraint(s) | Requested | Actual | Logic Levels |
All Constraints Met |
Report Name | Status | Last Date Modified |
Synthesis Report | Current | Sunday 03/27/05 at 12:24 |
Translation Report | Current | Sunday 03/27/05 at 12:24 |
Map Report | Current | Tuesday 03/29/05 at 08:18 |
Pad Report | Current | Tuesday 03/29/05 at 08:19 |
Place and Route Report | Current | Tuesday 03/29/05 at 08:19 |
Post Place and Route Static Timing Report | Current | Tuesday 03/29/05 at 08:19 |