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-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:55:23 07/17/2008 
-- Design Name: 
-- Module Name:    display_ctrl - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity event_counter is
  port(
        CPLD_CLK	: in std_logic;
		  ENABLE_COUNTER_IN : in std_logic;
		  RESET_COUNTER_IN : in std_logic;
		  ENTRY_SAVE_OUT : out std_logic_vector(15 downto 0)
		  );
end event_counter;

architecture count of event_counter is
  signal enable_counter : std_logic;
  signal reset_counter : std_logic;
  signal counter : std_logic_vector(15 downto 0);
begin

enable_counter <= ENABLE_COUNTER_IN;
reset_counter <= RESET_COUNTER_IN;

process (CPLD_CLK)
begin  
  if rising_edge(CPLD_CLK) then
    if reset_counter = '1' then
	  counter <= (others => '0');
	 else
     if enable_counter = '1' then
        counter <= counter +1;
	  end if;
	 end if;
  end if;
end process;


ENTRY_SAVE_OUT <= counter;

end count;