Design Overview for toplevel

PropertyValue
Project Name:e:\projects\tigersharc\ise\featureddesign\toplevel
Target Device:xc4vlx40
Constraints File:E:/Projects/TigerSharc/Ucf/FeaturedDesign/LinkPort.ucf
Report Generated:Thursday 10/20/05 at 20:56
Printable Summary (View as HTML)toplevel_summary.html

Device Utilization Summary

Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops:20136,8641% 
Number of 4 input LUTs:17236,8641% 
Logic Distribution:    
Number of occupied Slices:14618,4321% 
Number of Slices containing only related logic:146146100% 
Number of Slices containing unrelated logic:01460% 
Total Number 4 input LUTs:20936,8641% 
Number used as logic:172   
Number used as a route-thru:36   
Number used as Shift registers:1   
Number of bonded IOBs:17564027% 
Number of BUFG/BUFGCTRLs:43212% 
Number used as BUFGs:4   
Number used as BUFGCTRLs:0   
Number of FIFO16/RAMB16s:8968% 
Number used as FIFO16s:0   
Number used as RAMB16s:8   
Number of DCM_ADVs:2825% 
Number of BUFRs:1323% 
Number of ISERDESs:86401% 
Number of OSERDESs:56401% 
Number of IDELAYCTRLs:1224% 
Number of BUFIOs:1442% 
Number of RPM macros:3   

Performance Summary

PropertyValue
Final Timing Score:0
Number of Unrouted Signals:All signals are completely routed.
Number of Failing Constraints:0

Failing Constraints

Constraint(s)RequestedActualLogic Levels
All Constraints Met   

Detailed Reports

Report NameStatusLast Date Modified
Synthesis ReportCurrentThursday 10/20/05 at 20:54
Translation ReportCurrentThursday 10/20/05 at 20:54
Map ReportCurrentThursday 10/20/05 at 20:55
Pad ReportCurrentThursday 10/20/05 at 20:56
Place and Route ReportCurrentThursday 10/20/05 at 20:56
Post Place and Route Static Timing ReportCurrentThursday 10/20/05 at 20:56