| Property | Value |
| Project Name: | e:\projects\tigersharc\ise\featureddesign\toplevel |
| Target Device: | xc4vlx40 |
| Constraints File: | E:/Projects/TigerSharc/Ucf/FeaturedDesign/LinkPort.ucf |
| Report Generated: | Thursday 10/20/05 at 20:56 |
| Printable Summary (View as HTML) | toplevel_summary.html |
| Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Flip Flops: | 201 | 36,864 | 1% | |
| Number of 4 input LUTs: | 172 | 36,864 | 1% | |
| Logic Distribution: | ||||
| Number of occupied Slices: | 146 | 18,432 | 1% | |
| Number of Slices containing only related logic: | 146 | 146 | 100% | |
| Number of Slices containing unrelated logic: | 0 | 146 | 0% | |
| Total Number 4 input LUTs: | 209 | 36,864 | 1% | |
| Number used as logic: | 172 | |||
| Number used as a route-thru: | 36 | |||
| Number used as Shift registers: | 1 | |||
| Number of bonded IOBs: | 175 | 640 | 27% | |
| Number of BUFG/BUFGCTRLs: | 4 | 32 | 12% | |
| Number used as BUFGs: | 4 | |||
| Number used as BUFGCTRLs: | 0 | |||
| Number of FIFO16/RAMB16s: | 8 | 96 | 8% | |
| Number used as FIFO16s: | 0 | |||
| Number used as RAMB16s: | 8 | |||
| Number of DCM_ADVs: | 2 | 8 | 25% | |
| Number of BUFRs: | 1 | 32 | 3% | |
| Number of ISERDESs: | 8 | 640 | 1% | |
| Number of OSERDESs: | 5 | 640 | 1% | |
| Number of IDELAYCTRLs: | 1 | 22 | 4% | |
| Number of BUFIOs: | 1 | 44 | 2% | |
| Number of RPM macros: | 3 |
| Property | Value |
| Final Timing Score: | 0 |
| Number of Unrouted Signals: | All signals are completely routed. |
| Number of Failing Constraints: | 0 |
| Constraint(s) | Requested | Actual | Logic Levels |
| All Constraints Met |
| Report Name | Status | Last Date Modified |
| Synthesis Report | Current | Thursday 10/20/05 at 20:54 |
| Translation Report | Current | Thursday 10/20/05 at 20:54 |
| Map Report | Current | Thursday 10/20/05 at 20:55 |
| Pad Report | Current | Thursday 10/20/05 at 20:56 |
| Place and Route Report | Current | Thursday 10/20/05 at 20:56 |
| Post Place and Route Static Timing Report | Current | Thursday 10/20/05 at 20:56 |