Property | Value |
Project Name: | e:\projects\tigersharc\ise\regulardesign\toplevel |
Target Device: | xc4vlx40 |
Constraints File: | E:/Projects/TigerSharc/Ucf/RegularDesign/LinkPort.ucf |
Report Generated: | Thursday 10/20/05 at 21:06 |
Printable Summary (View as HTML) | toplevellinkport_summary.html |
Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Flip Flops: | 267 | 36,864 | 1% | |
Number of 4 input LUTs: | 180 | 36,864 | 1% | |
Logic Distribution: | ||||
Number of occupied Slices: | 189 | 18,432 | 1% | |
Number of Slices containing only related logic: | 189 | 189 | 100% | |
Number of Slices containing unrelated logic: | 0 | 189 | 0% | |
Total Number 4 input LUTs: | 242 | 36,864 | 1% | |
Number used as logic: | 180 | |||
Number used as a route-thru: | 45 | |||
Number used for Dual Port RAMs: | 16 | |||
Number used as Shift registers: | 1 | |||
Number of bonded IOBs: | 161 | 640 | 25% | |
Number of BUFG/BUFGCTRLs: | 3 | 32 | 9% | |
Number used as BUFGs: | 3 | |||
Number used as BUFGCTRLs: | 0 | |||
Number of FIFO16/RAMB16s: | 8 | 96 | 8% | |
Number used as FIFO16s: | 0 | |||
Number used as RAMB16s: | 8 | |||
Number of DCM_ADVs: | 2 | 8 | 25% | |
Number of BUFRs: | 1 | 32 | 3% | |
Number of BUFIOs: | 1 | 44 | 2% | |
Number of RPM macros: | 30 |
Property | Value |
Final Timing Score: | 986 |
Number of Unrouted Signals: | All signals are completely routed. |
Number of Failing Constraints: | 0 |
Constraint(s) | Requested | Actual | Logic Levels |
* TS_03 = PERIOD TIMEGRP "RxClk" 400 MHz HIGH 50% | 2.500ns | 2.954ns | 3 |
Report Name | Status | Last Date Modified |
Synthesis Report | Current | Thursday 10/20/05 at 21:04 |
Translation Report | Current | Thursday 10/20/05 at 21:04 |
Map Report | Current | Thursday 10/20/05 at 21:05 |
Pad Report | Current | Thursday 10/20/05 at 21:06 |
Place and Route Report | Current | Thursday 10/20/05 at 21:06 |
Post Place and Route Static Timing Report | Current | Thursday 10/20/05 at 21:06 |