Design Overview for toplevellinkport

PropertyValue
Project Name:e:\projects\tigersharc\ise\regulardesign\toplevel
Target Device:xc4vlx40
Constraints File:E:/Projects/TigerSharc/Ucf/RegularDesign/LinkPort.ucf
Report Generated:Thursday 10/20/05 at 21:06
Printable Summary (View as HTML)toplevellinkport_summary.html

Device Utilization Summary

Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops:26736,8641% 
Number of 4 input LUTs:18036,8641% 
Logic Distribution:    
Number of occupied Slices:18918,4321% 
Number of Slices containing only related logic:189189100% 
Number of Slices containing unrelated logic:01890% 
Total Number 4 input LUTs:24236,8641% 
Number used as logic:180   
Number used as a route-thru:45   
Number used for Dual Port RAMs:16   
Number used as Shift registers:1   
Number of bonded IOBs:16164025% 
Number of BUFG/BUFGCTRLs:3329% 
Number used as BUFGs:3   
Number used as BUFGCTRLs:0   
Number of FIFO16/RAMB16s:8968% 
Number used as FIFO16s:0   
Number used as RAMB16s:8   
Number of DCM_ADVs:2825% 
Number of BUFRs:1323% 
Number of BUFIOs:1442% 
Number of RPM macros:30   

Performance Summary

PropertyValue
Final Timing Score:986
Number of Unrouted Signals:All signals are completely routed.
Number of Failing Constraints:0

Failing Constraints (total failing = 1)

Constraint(s)RequestedActualLogic Levels
* TS_03 = PERIOD TIMEGRP "RxClk" 400 MHz HIGH 50% 2.500ns2.954ns3

Detailed Reports

Report NameStatusLast Date Modified
Synthesis ReportCurrentThursday 10/20/05 at 21:04
Translation ReportCurrentThursday 10/20/05 at 21:04
Map ReportCurrentThursday 10/20/05 at 21:05
Pad ReportCurrentThursday 10/20/05 at 21:06
Place and Route ReportCurrentThursday 10/20/05 at 21:06
Post Place and Route Static Timing ReportCurrentThursday 10/20/05 at 21:06