List of patches compiled by Marcin on 06.05.2005
Error list in order of tracing them:
- RESET is output from ETRAX
- MRESET is input to ETRAX (place manual switch?)
- Ethernet connector connect pin P4 to 3.3V
- Connect RD, WE ETRAX signals to Spartan
- Connect PHY_RESET directly to RESET output of ETRAX
- DC/DC should not be close to TDC
- LED D25 on the bottom side
- JTL connectors should have keep-out area
- Two single switches instead of switch1, and a connector which allows to contol this state via an external voltage (for example HahShoPoMo)
- Missing JTAG connector for programming Spartan and TDC via cable
- Schmidt trigger BGA chip in between two big capacitors
- two different via diameters on the board
- clock 20 MHz should not come from CPLD
- DPRAM: CNTRST = 1, (then CNTEN =1 or 0, does not matter)
- some JTL connectors are face-to-face no way to plug flat cable to both of them
- DPRAM speed grade should be -7 (or at least -9)
- ETRAX should be able to reset TDCs
- TDC_CLOCK_ENABLE signal also controls clock to one of DPRAM
- TDC_C JTAG lines swapped
- CPLD TDC JTAG add pull-up resistors
- LVDS resistors are not close to Spartan LVDS inputs
- TRIGGER, BUNCH_RESET and EVENT_RESET fan-out (TRIGGER should use free U16 outputs, bunch and event reset need next CDCLVD110 chip)
Mail from Marcin:
Date: Fri, 24 Jun 2005 09:42:48 +0200 (METDST)
From: Nowoczesna Elektronika <email@example.com>
To: Michael Traxler <M.Traxler@gsi.de>
Cc: Krzysztof Korcyl <Krzysztof.Korcyl@ifj.edu.pl>
Subject: Re: CPLD conf file on hades17:/tmp/jtag_readout.jed
We have found a possible reason of problems with your board. We
have added a wire connection between U8 CPLD pin C5 (diode D15) and
RESET switch S3 pin 3 (resistor R318). This makes possible doing reset of
TDCs and FIFO from FPGA (via CPLD).
Kris will skype you later today.
Bugs found during beam-test Nov2005
- There is a bug in the schematics: Device U12A, the pin 9A (27) has to be lifted as it otherwise will drive against GND.
- Busy and Error signal on Trigger-Bus can not be tristated. This prevents us from using a trigger BUS, we can only use point to point connections.
- Trigger Bus should have a switch to turn on or off the termination-resistors.
- The dual-ported ram should be a FIFO, as there is no need for a DP-RAM and an FIFO is much easier to use.
- The TriggerBus should have one large connector for all 20 pairs, as there is no need to separate them
- Proposal: Usage of high density cable, VHDCI connectors and cables, standard in IT-technology (SCSI), 8 connectors (68 pins) would fit in one VME-front-panel, for LVL1 and LVL2 at once. Cables can be bought in length upt to 10m (90). Or we can use the same cable and connectors as for the RPC-FEE signals, KEL 40 pins, and standard bus-technology, so IDC cabling.
- Take care that the trigger-timing signal has the correct polarity. On the current board U16 uses switched clock inputs.
- Using new technology switching power supply: PME5218TS (same kind for all voltages)
- Shielding of 48V power supply, usage of new 48V DC/DC converter technology from C&D
- take care that the 48V are really galvanically isolated
- more ground pads for connection to detector
- 09 Nov 2005