List of patches compiled by Marcin on 06.05.2005

Error list in order of tracing them:

  1. RESET is output from ETRAX
  2. MRESET is input to ETRAX (place manual switch?)
  3. Ethernet connector connect pin P4 to 3.3V
  4. Connect RD, WE ETRAX signals to Spartan
  5. Connect PHY_RESET directly to RESET output of ETRAX
  6. DC/DC should not be close to TDC
  7. LED D25 on the bottom side
  8. JTL connectors should have keep-out area
  9. Two single switches instead of switch1, and a connector which allows to contol this state via an external voltage (for example HahShoPoMo)
  10. Missing JTAG connector for programming Spartan and TDC via cable
  11. Schmidt trigger BGA chip in between two big capacitors
  12. two different via diameters on the board
  13. clock 20 MHz should not come from CPLD
  14. DPRAM: CNTRST = 1, (then CNTEN =1 or 0, does not matter)
  15. some JTL connectors are face-to-face no way to plug flat cable to both of them
  16. DPRAM speed grade should be -7 (or at least -9)
  17. ETRAX should be able to reset TDCs
  18. TDC_CLOCK_ENABLE signal also controls clock to one of DPRAM
  19. TDC_C JTAG lines swapped
  20. CPLD TDC JTAG add pull-up resistors
  21. LVDS resistors are not close to Spartan LVDS inputs
  22. TRIGGER, BUNCH_RESET and EVENT_RESET fan-out (TRIGGER should use free U16 outputs, bunch and event reset need next CDCLVD110 chip)

Mail from Marcin:
Date: Fri, 24 Jun 2005 09:42:48 +0200 (METDST)
From: Nowoczesna Elektronika <>
To: Michael Traxler <>
Cc: Krzysztof Korcyl <>
Subject: Re: CPLD conf file on hades17:/tmp/jtag_readout.jed

Hello Michael,
        We have found a possible reason of problems with your board. We
have added a wire connection between U8 CPLD pin C5 (diode D15) and
RESET switch S3 pin 3 (resistor R318). This makes possible doing reset of
TDCs and FIFO from FPGA (via CPLD).
        Kris will skype you later today.
        Cheers, Marcin

Bugs found during beam-test Nov2005

  • There is a bug in the schematics: Device U12A, the pin 9A (27) has to be lifted as it otherwise will drive against GND.
  • Busy and Error signal on Trigger-Bus can not be tristated. This prevents us from using a trigger BUS, we can only use point to point connections.
  • Trigger Bus should have a switch to turn on or off the termination-resistors.
  • The dual-ported ram should be a FIFO, as there is no need for a DP-RAM and an FIFO is much easier to use.
  • The TriggerBus should have one large connector for all 20 pairs, as there is no need to separate them
  • Proposal: Usage of high density cable, VHDCI connectors and cables, standard in IT-technology (SCSI), 8 connectors (68 pins) would fit in one VME-front-panel, for LVL1 and LVL2 at once. Cables can be bought in length upt to 10m (90). Or we can use the same cable and connectors as for the RPC-FEE signals, KEL 40 pins, and standard bus-technology, so IDC cabling.
  • Take care that the trigger-timing signal has the correct polarity. On the current board U16 uses switched clock inputs.

Other improvements

  • Using new technology switching power supply: PME5218TS (same kind for all voltages)
  • Shielding of 48V power supply, usage of new 48V DC/DC converter technology from C&D
  • take care that the 48V are really galvanically isolated
  • more ground pads for connection to detector

-- MichaelTraxler - 09 Nov 2005
Topic revision: r5 - 2009-10-27, JanMichel
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