Things we learned from Etrax_FS_Dev1

1. A Ceramic Capacitor (100V) on 48V is missing (100nF).
2. Take care of the LEDs. They are not correct on the ETRAX_FS_DEV1
3. The ispPower-device has to be on a seperate JTAG chain, because the chain will be disrupted when the isp-Power-Chip turns off the power of the ETRAX-FS, which is in the same chain! Not true, the ispPower has the TDISELECT-pin to chose a different TDI pin. everything is perfectly correct in the ETRAX_FS_DEV1 as long as the ispPower is the last device in the JTAG-chain.
4. The stupid Xilinx-Impact software doesn't allow to program "alien" parts (I (MT) had a conversation with Lattice and Xilinx Engineers). So, we are forced to use a Lattice cable for the clock and power chip. I already ordered a cable (2006-06-28). Then we should forsee on the TRBV2 a simple standard pin-header with the clock and power chips from lattice in this chain.
5. The ispClock chip should have a pi-filter with ferrite bead at least on the AVDD-pins (e.g. BLM18BA050SN1B)
6. The schematics should contain in very big letters the purpose of the sheet, like "CLOCK". (see IPU_LINK: connector)
7. The KW010A needs the remote pin to be pulled down, so J8 should have a 0Ohm to GND.
8. please use decriptive but short (less than 8 characters with number) names on the part designators where applicable.
9. If possible, most of the nets should have names to avoid searching for N134234231 on the layout..
10. The TLK2501 needs a 10uF cap at VCC_R.
11. It would be nice to have the reference clock shifted by 25ps from each TDC to the next, to have a better time resolution.
12. Power LEDs are only working down to 2.5V (also barely working). 5 LEDs are really to much! So, one LED for 5V and one LED from the ispPowerChip is enough, which would be an and of all voltages.
13. The Jumper for BS6 of the EtraxFS should be set to 16-bit flash and not 32-bit flash