## README
## $Source: /var/www/hades-wiki.gsi.de/data/DaqSlowControl/MatchingUnitExperts.txt,v $
## $Id: MatchingUnitExperts.txt,v 1.6 2006/04/21 08:45:52 HadesDaq Exp www-data $
## This README describes some important registers in the Matching Unit V1.0 (Prototyp)
StatusInfo:
printf_daemon 0xd2004000
LVL1 and LVL2 rate:
viewrate d00E800C d00E8014
viewrate d00e800c d00e8014 d00e808c d00e8098 d00e80e4 d00e80a8
Read Register:
rw r <address>
Write Register:
rw w <address> <value> # all hexadecimal
Read the number of LVL2 Trigger decisions:
rw r d00E800C
Register: Function: Remark:
-------------------------------------------------------------------
d00E8000 RICH hand addressing here you can *write* (only) the address which should be sent over the RICH IPU-bus (1-6)
d00E8004 SHOWER hand addressing " (1)
d00E8008 TOF hand addressing " (1-3)
d00E800C LVL1 Triggers number of triggers received from IPUs, read only
d00E8010 MU Status register read only
d00E8018 LVL2 Busy Counter der steht am anfang auf 100(dec), den kannst Du durch
beschreiben auf andere Werte setzten, um die Effekte
des Delay zu testen. (Achtung: hex werte)
d00E8014 DAQ event counter Number of events sent to DAQ
d00E801C debug flag printf_vme information, set to 0 to stop debug info
bit 3-0: debug level of data transport
bit 7-4: debug level of matching algorithm
d00E8020 not_connected_ipu_reg this register is to mask out IPUs which sould not be used
to make a LVL2 Trigger decission.
bit 0: RICH
bit 1: SHOWER
bit 2: TOF
d00E8024 pos_trigger_cond_mask bit 0: reduction
bit 1: RICH
bit 2: SHOWER
bit 3: TOF
0x01 => feste untersetzung
0x02 => mask out rich, test tag of shower tof IPU
0x06 => mask out rich, and shower, test tag of tof IPU and MU
d00E80A0 always_negative_flag MU algo. is turned off, downscaling still works
d00E8028 lvl2_trigger_rate reduction value, downscaling
d00E8030 pos_trigger_by_hand just write something other than 0 to it, to make a
2LVL trigger
d00E8034 global_dma_flag 0=dma off, 1=dma on
d00E8040 global_error_message_flag 0=off 1=on [default]
d00E8064 glob_send_trigger_to_CTU_flag 0=off, 1=on
d00E8078 global_CTU_BUSY_wait_register
d00E808C g_trigger_cond_1_met counter
d00E8090 g_trigger_cond_2_met counter
d00E8094 g_trigger_cond_3_met counter
d00E8098 g_trigger_cond_4_met counter
d00E809C g_trigger_cond_5_met counter
d00E80CC G_CLEAR_IPU_RECEIVE_MEMORY set this to 1, if you want the IPU receive
memory to be cleared in every event
d00E8058 Number of last addressed RICH-IPU
d00E805C Number of last addressed SHOWER-IPU
d00E8060 Number of last addressed TOF-IPU
d00E80D0 G_TOTAL_WORDS_RICH The total number of 32-bit words received from
the RICH-IPU
d00E80D4 G_TOTAL_WORDS_SHOWER
d00E80D8 G_TOTAL_WORDS_TOF
d00E80DC G_TOTAL_WORDS_MU
d00E80E0 G_TOTAL_WORDS
d00E80E4 G_ACCUMULATED_RICH_HITS
Trigger conditions:
d00E80B0 Number hits in Rich
d00E80B4 Number hits in Meta
d00E80B8 Number leptons
d00E80BC Number di-leptons
d00E807C Delta-Phi Window size: 0 => 0 degrees, 0xff => 60 degrees
d00e8104 Delta-Phi slope parameter:
rich_phi in half sector (0 to 30) / 2^parameter
d00E8138 RAND_DOWNSCALE_MASK
d00E813C RAND_DOWNSCALE_VALUE
For 1:4 random downscaling put 0x3 to RAND_DOWNSCALE_MASK
1:8 => 0x7
1:16 => 0xf
....
....
For checking the data received from the IPUs:
RICH:
/bin/ces/vdump d00CC000 20
Shower:
/bin/ces/vdump d00CC800 20
TOF:
/bin/ces/vdump d00CD000 20
vdump only available for RIO.
use "rw_dump" for Concurrent-CPUs
#####################################
# Status Registers for Matching Unit
#
######################################
Status Reg. 1
0x00000001 read_link_buffer_to_fifo delayed due to fifo almost full flag
0x00000002 send_result_to_DAQ delayed due to fifo almost full flag
0x00000004 write_nibble_to_ctu delayed due to CTU busy flag
0x00000008 event was much too long, hang forever
0x00000010 global stop flag
-------------------------------------------
-------------------------------------------
--------------------
Addresses and bits:
--------------------
d6dead00: setup
7 6 5 4 3 2 1 0
Enable_Fifo_clock /SELF_DATA /Fifo_Reset /IPU_FIFO_RES /SH_RES /SBTS
d6dead08: Status Register
7 6 5 4 3 2 1 0
Fifo_P_AE Fifo_EF Fifo_P_AF Fifo_FF CTU_busy_signal
d?0e8000: IPU addressing
7 6 5 4 3 2 1 0
link speed IPU_address
Checking LVL2 CTU Fifo Full counter + rich poll counters 0 and 1
viewrate d00e8078 d00c5c64 d00c5c68
restart stuck TOF chained-DMA
rw w d00000ec 09137
--
MichaelTraxler - 28 Jan 2005