CTS and Trigger Logic addresses

To all register when accessing vi trbnet add offset A0

CTS

Address	Bit range	Meaning
91	15 downto 0	lvl1 trigger number
91	19 downto 16	lvl1 trigger code
91	20	lvl1 cts busy
91	21	lvl1 trbnet busy
91	22	lvl1 local busy
91	23	lvl1 trigger box busy
91	31 downto 24	lvl1 trigger random code
92	19 downto 0	lvl1 trigger rate (accepted triggers/s)
92	20	apv double pulse busy (RICH)
92	21	lvl1 self trigger
92	25 downto 22	event rate cntr(7,9,11,13) - for diods
92	26	lvl2 cts busy
92	27	lvl2 trbnet busy
92	28	lvl2 local busy
93	0	CTS fifo full b(for random numbers)
93	1	CTS fifo empty b
93	2	CTS fifo full a (trigger code and number)
93	3	CTS fifo empty a
93	11 downto 4	lvl1-lvl2 : difference counter
93	23 downto 12	lvl2 trigger number (11 downto 0)
93	31 downto 24	CTS fifo data counter a
c3	4	disable readout on etrax
c5	15 downto 0	enable individual triggers: (4 downto 0) - LVDS(4 downto 0) - corresponds to ado_lv(9 downto 0) on the trbv2 schematics (9 downto 5) - LVTTL(20 downto 16) - corresponds to ado_ttl(20 downto 16) on the trbv2 schematics (10) trigger form fast reference trigger - corresponds to Vir_Trig on the trbv2 schematics (11) self triggering (internal generator) (12) coincidence LVDS(0) and LVDS(1) (13) Trigger from C5(28) register (14) coincidence LVTTL(0) and LVTTL(1) (15) coincidence LVTTL(2) and LVTTL(3) Depends which input is enabled there is corresponding trigger code 0 - x0xf , 1 - x0xe, 2 - 0xd ...
c5	17 downto 16	change source of LVL2 trigger: "00" - auto "01" - LVDS lines "10"- local source
c5	27 downto 20	how many LVL1 trigger has to pass to send LVL2 trigger
c5	28	trigger on rising edge
c5	29	not used
c5	30	enable connection to trigger box
c5	31	make double APV pulse
c6	7 downto 0	LVL2 downscale
c6	27 downto 8	frequency of self triggering : 50MHz/value
c6	31 downto 28	length of timing trigger : 100ns + value*10ns (when is value< 7), when value > 6 time = (value - 7) * 10ns
c7	4 downto 0	if c7(4)=1 the lvl1 trigger type equals c7(3 downto 0) else type is defined internally or by trigger box
c8	13 downto 0	lvl1 trigger information 13 downto 0
c9	31 downto 0	how many events is send before next ID of IP address is changed, when equals 0 then default is taken from c10(3 downto 0)
c11-c10	all bits divided into nibles	First nible ( c10(3 downto 0) ) is the first ID of the EB IP and so on (16 IDs)

Address range from 0x80 to 0xBF is for read only registers above 0xc0 is for read/write registers.

APV signal is on ADO_LV 52(positive) and 53(negative)
Timing trigger out: ADO_LV 54(p) 55(n)
lvl1 busy out ADO_LV 56(p) 57(n)
lvl2 busy out ADO_LV 58(p) 59(n)
40 MHz clock out ADO_LV 60(p) 61(n)

HADES Trigger Logic

Address	Bit range	Meaning
cc	31 downto 0	input enables
d0 c16 - c13	all bits	downscale, each nibble corresponds to one input
d4 - d1	all bits	width, each nibble corresponds to one input
d9	31 downto 0	TS gating disable
da	31 downto 0	trigger out enable
db	23 downto 0	multiplexer out selsect
dc	4 downto 0	if c28(4)=0 then normal trigger selection else trigger code = c(28)(3 downto 0)
dc	5	MDC callibration trigger disable
dc	6	Force Shower calibration trigger
dc	7	Enable daily Shower calibration trigger
dc	11 downto 8	Select frequency for generated trigger,781.25kHz/(2^value)
89	-	trigger logic debug out
9a -bb	all bits	scalers out

More detailed description can be found : .... (pdf files)

Other settings

Address	Bit range	Meaning
c8	13 downto 0	trigger information in
cb - ca	all 32 bits	IP LUT each nibble corresponds to given IP address, the CTS is deciding to which EB current event should go (round robin)

How to start readout on CTS with DMA readout

Ensure You have newest kernel : hadeb05:~/soft/devboard-R2_20/.
If you have it then run following commands :
killall readout_dma
rmmod readoutdma_module
/home/hadaq/jamv2_reg -aRUN_XILINX_PROC /home/hadaq/develop_board/hades_cts_trb.stapl
rw_portA w 0x0000
rw_portB r
rw_portC r
insmod /home/hadaq/readoutdma_module.ko
sleep 2
readout_dma -w 10000 -o UDP:$eb_ip:34068 &
sleep 4
rw_trbv2 w 0 c4 0x35f
sleep 10

rw_trbv2 w 0 c2 80000000 # ads header (it will be removed - not necessary )
rw_trbv2 w 0 c3 00000100 # enable blinking diods
rw_trbv2 w 0 c6 8000
rw_trbv2 w 0 c5 800

All files can be founf on :
lxhadesdaq:/var/diskless/etrax_fs/
lxhadesdaq:/var/diskless/etrax_fs/bin
lxhadesdaq:/var/diskless/etrax_fs/develop_board

In case of bugs , problems, questions contact with Marek : m.palka@gsi.de

-- MarekPalka - 20 Jul 2009