General IO interface
To make the DaqNetwork
independent from any media, a standard IO interface is proposed.
The interface follows the principle, that data words are never pushed into the next stage, but always offered and
read be the next stage. In detail, the interface should look like:
|| Data word is reconstructed and ready to be read out by the internal logic
|| Data word
|| Internal logic is reading from the FIFO
|| Status bits
|| Data word is offered by the internal logic or FIFO
|| Data word
|| Media interface reads a word
(the INT_ERROR_OUT will be used only for the 1st output)
As one can see, there are 2 symmetric directions: One for the direction to the internal logic,
one for the data direction to the media. All entities of the DaqNetwork
should follow this
principle (sometimes however one one-directional, and the width "DATA_WIDTH" might change)
The 8 missing spare bits to complete 64Bit might use for additional error detection/correction if needed.
Meaning of the error bits:
|| Data word OK
|| Transmission error from the 8B/10B encoding
|| Transmission error, reconstructed by additional bit
|| Fatal error, not recoverable
|| Media not connected
To avoid the big register logic of all entities which are using really big
buses, the generic "SLICES" should be used.
- SLICES=0: Do not use slices, only the big bus
- SLICES>0: Scramble the bus into several slices
In addition, the generic "BUS_WIDTH" has to be used. It is very clear, that for the SLICES=0 the BUS_WIDTH have to match the
DATA_WIDTH. Otherwise, the bus bits have a different meaning: The first bits are the slice number, so if SLICES=4 (matching to 100MHz with the optical link), 2 bits are needed. In addition, for 56 data bits, 14 bus bits are needed in addition. This makes 16 bits!
The use of an optical links has many advantages:
- No charge flow
- Long cable connections (1km!)
- Standard technologie (SFP), many vendors
We will use the TLK2501/TLK1501 as a Serdes chip: 16 Bit data bus, error and link detection makes debugging much easier.
In addition, the 8B/10B encoding allows to send special symbols, like commas, carier extend, errors. This allows
to separate the frames and synchronize state machines of the transmitter and receiver.
The frame content of the NewTriggerBusNetwork
is always fixed on 64Bit (with 56Bit needed data bits for the protocol),
thus it makes the decoding very easy. In addition the 8 remaining bits could used the protect
the most important 2*4 Bits (transported in 4 TLK frames) using the 4-7 Hamming code.
These bits can even be reconstructed if a word is completely corrupted, the
data content is then lost, but who cares...
SCSI cable and trb add-on lvds links.
A standard SCSI cable is used for the connection of the AcromagModule
. From the 32 IO lines, 16 lines are used for each direction.
As it can be seen, with 13 data bits, 65 data bits can be transferred in 5 frames (9 bits can be used for error checking and correction).
"carrier" is 1 for data words, and 0 for control words (like idle), needed for frame synchronization.
Parity can be used for additional error detection.
The order of the signal on the cable or the addon connector depend on the clk input pins and might differ for the 2 cases.
Advantage: 4 twisted pair lines, off-the-shelf cables
Two pairs can be used for downstream (to the endpoints), and 2 for upstream (to the master). This allows to use always one line for clock (if needed) and one for data. LVDS signals should be used, the clock frequency should be choosen that 100m cables could be used.
|| Color of Line
|| white to green
|| white to orange
|| white to blue
|| white to brown
The use of the signals in this way makes sure that even if by accident a crosover cable is used, only CLK and DATA of one direction is mixed.
- 20 Nov 2006