Not the official milestones, but some pragmatic steps:
VHDL simulation done by Ingo. First important step is to have a running chain with 2 dummy APLs sending, the complete IOBUFs in between, and the lvds link written by Jan Michel. Simulation seems to be OK (2.3.2007): LVDS is running with 25MHz (slow interface)
* lvds chain:
- 14 Feb 2006
Tests with hardware
07.05.2007: The communication between the acromag and the TRB test board is running stable now. The acromag contains a simple APL that sends data (it counts from 0 to 5) to the TRB which acknowledges and answers each transfer. Both FPGA are running at 100 MHz while the LVDS transfer has a clock of 25 MHz.
- 07 May 2007
16.10.2007: 16 bit version of the network almost finished. A first test of the new entities in hardware has been done.
A sample transfer on a 8Bit LVDS cable with trb_net16:
- 25 Oct 2007
Tests on the optical link and TLK1501
- Get first communication with the acromag design running
- Make a hub base design
- Connect the modules to a loopback device:
- Test interrupts
- Implement software DTU
- Make connection from DTU to software TIP
Connection with the TRB-test board
The TRB test board will have 2 optical links, one SCSI link to connect the AcromagModule
and might serve as an old-to-new converter.
In this sense, it is a TRB-Net-Hub