Minutes of TRB Meeting 2005-05-31

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Attendees:

Wolfgang Koenig, Marcin Kajetanowicz, Ingo Frhlich, Michael Traxler, Piotr Salabura, Jerzy Pietraszko

Topics:

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Status of current TRB ("TDC Readout Board") prototype:

• No severe known bug, all components are accessible
• Times can be measured, but at the moment only be read-out reliably via JTAG (slow). The normal data bus sends corrupted data (but sends data!). Seems to be a configuration problem of the TDCs or an VHDL-bug in the read-out-FPGA (more likely!).
• Hades-Trigger-Bus VHDL-code of Tiago still has to be deployed/tested (Kris, Tiago)
• HADES-compliant-Readout-code still has to be implemented (compiled on the ETRAX-chip [Radek])

Time schedule:

• approx. 3 weeks debugging for TDC-FPGA-readout-problem (Kris, Marcin)
• 4 weeks in July: Radek will implement the HADES-compliant-Readout-code
• We will ask Tiago Perez to compile and download (and basic tests) the VHDL DTU-core code to the TRB. This will happen after Dubna (Tiago [to be confirmed], Ingo, Michael)
• Connecting the Tiago-Trigger-Bus VHDL-code to existing TRB-VHDL code. Kris: in July (?, to be confirmed)

After this tasks the TRB will be usable. In July Marek Palka and Radek Trebazk can start a comprehensive test-series with it (July till September).

Wolfgangs remark:

Date: Mon, 6 Jun 2005 14:18:06 +0200 From: Koenig Wolfgang <W.Koenig@gsi.de> To: HADES-RPC@LISTSERV.GSI.DE Subject: AW: Minutes of TRB Meeting 2005-05-31

Hello, regarding modifications of the TRB board we forgot to discuss a test signal to be send to the motherboard in case of a calibration trigger. Distribution on the motherboard (LVDS) is already implemented. A 4 fold Fan-Out chip with (2 groups of 2 signals) allows to enable individually odd and even Test inputs to the daughterboards. Thus, one needs one LVDS pair for the test signal and two (eg. TTL) signals for the more or less static routing of the test signal. Details to be discussed with Soeren.

Wolfgang

-- MichaelTraxler - 13 Jul 2005