Here we describe our various AddOn Cards for the TRBv2
HUB-AddOn
The TRB-HUB servers as the trigger fanout-module.
It has 16 times a 2-GBit/s SFP. The SERDESes are in the LatticeSCM40 FPGA.
Fully impedance matched 12-layer PCB.
ShowerAddOn
The features of the ShowerAddOn alias General-Purpose-ADC-AddOn
- 96 channels 10-bit ADCs
- 40/60 MSPS
- ADC type: AD9212 from Analog Devices
- low noise, variable gain amplifier at the input (AD8334 from Analog Devices)
- input voltage range: 275 mV (AC coupled),
- -3 dB bandwidth: 100 MHz (independent on gain)
- amplifier noise: 0.74 nV/sqrt(Hz), 2.5 pA/sqrt(Hz)
- Two 68-pin connectors, each connector contains:
- 48 analog inputs,
- 5 LVDS lines (programmable direction)
- 2 TTL lines (programmable direction)
- +5V (2 pins), GND (6 pins).
- Connector type: HDRA-EC68LFDT-SL from Honda Connectors
FPGA: LFE2-70E-5F900C from Lattice
Schematics are finished, layout is finished, we are waiting for the PCB (2008-02-05).
The General Purpose Add on: Short Description
The General Purpose Add on (GP-AddOn) board povides the interface between the TRBv2 (main readout board) and many different signals.
For example it can used as interface to the old HADES trigger bus.
The GP-AddOn can be easily connected to the TRBv2 board through 2 connectors (QSE-040-01) placed on the back side of the board. The power supply is given to the GP-Addon through the connector's pins.
A programmable logic CPLD (
XCR3128XL7VQ100C) is placed on the right hand side and is supported by Xilinx Web-PACK and industry standard CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor, Synopsys, Viewlogic, and Synplicity), using HDL editors with ABEL, VHDL, and Verilog.
Design verification uses industry standard simulators for
functional and timing simulation.
Here we attach the data sheets for further details of the board's component:
General Purpose addon board: front view
General Purpose addon board: back view
General Purpose addon board: block diagram
Pinouts and connectors
--
AttilioTarantola - 09 Oct 2006