Children of TRBvIIHowTo in DaqSlowControl Web

Results from DaqSlowControl web retrieved at 14:36 (Local)

DescriptionOfEtrax
spi for Tof This site is still waiting for Marek :)
r5 - 2008-10-24 - 10:42 by RadekTrebacz
DescriptionOfFPGA
A VIRTEX4 LX40 FPGA is used on the TRBv2. FPGA registers r/w adress bits r 0 31 26 not used ADO_LV 25 0 r 1 31 lvl2 busy 30:lvl1_fif...
r8 - 2008-07-23 - 17:14 by MarekPalka
DescriptionOfTDC
TDC is connected with FPGA thru two interfaces: * JTAG * Parallel JTAG interface It is used for programming status register and control register of TDC's...
r3 - 2007-07-24 - 15:43 by MarekPalka
GeneralDescription
How to start 1. Below you can find images for TRB. If you cannot find your image, mail to Radek(rtrebacz #64;gmail.com). Lets include information about NFS ser...
r11 - 2007-11-27 - 10:26 by RadekTrebacz
HowToPrepareServerForTrb
This page tries to explain how to prepare server to handle trb version2. assumptions: 1. server has ethernet interface eth0 with IP: 192.168.0.1 1. trb has...
r3 - 2009-10-27 - 19:08 by JanMichel
TRBTigerSHARC
TigerSHARC PIN Number of CMOS PINs Comments PINs connected to Virtex4 SCLKRAT 3 PLL muliplier, can be hardwired to 000 at 125MHz 0 SCLK 1...
r2 - 2009-10-27 - 11:45 by JanMichel
Number of topics: 6
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