TRBNet Files

Low level parts

Fifos

trb_net_fifo

A standard fifo entity. The architecture is not included for compatibility reasons.

xilinx/trb_net_fifo_arch

The fifo architecture to be used on xilinx virtex 2 / 4 devices.

xilinx/shift_lut_x16

instantiation of a xilinx 16bit shift register used for the fifo

trb_net_fifo_16bit_bram_dualport

A dualport fifo entity using a block ram. It has two separated clocks for reading and writing. At the moment it is only used for the lvds media interface

xilinx/trb_net_fifo_16bit_bram_dualport_arch

The architecture for xilinx virtex 2 / 4 devices.

trb_net_dummy_fifo

Behaves like a fifo but has a depth of one. Can be used instead of a real fifo when none is needed. It is used when a fifo with a depth of 0 is instantiated.

Converters

trb_net_18_to_16_converter
trb_net_55_to_18_converter
trb_net_64_to_18_converter

These are converters between different bus widths. They are not needed in any final design.

Others

trb_net_std

package with some fundamental definitions. Has to be included in nearly any other file.

dualdatarate_flipflop

A dual data rate flipflop entity. It is used for the fast lvds transmission

xilinx/dualdatarate_flipflop_arch

The xilinx architecture for a ddr flipflop

trb_net_sbuf

An output buffer using two buffers to be independent from the following part and don't have to take care whether it is reading the offered data or not.

Medium layer

trb_net16_med_8bit_slow

data transport over a 2 x 16 Bit wide bus, i.e. lvds. The data is transmitted with 25 MHz and 8 bits in parallel. five lines are used for control signals, three are free for debugging purposes.

Network layer

Multiplexer

trb_net16_io_multiplexer

A demultiplexer that divides the incoming data to the different ibufs according to channel id and path. Plus a multiplexer that combines the data from the obufs to the single media output, taking care of the different priorities of the different channels.

trb_net_pattern_gen

A combinatorial entity, takes a number and sets this bit in the output vector

trb_net_priority_arbiter
trb_net_priority_encoder

These entities take care of the priorities of the different channels and select the one with highest priority.

IOBUF

trb_net16_ibuf

The input buffer. Receiving data from the medium. Reads flow control packets and hands data to the api.

trb_net16_obuf

The output buffer. Sending data from the application layer, adding network layer packets

trb_net16_iobuf

The combination of ibuf and obuf, giving complete flow control for the network channel

trb_net16_term_ibuf

Simple type of input buffer to be used to receive triggers.

Hub

trb_net16_hub_base

base file for all hubs

trb_net16_hub_logic

the logic used inside a hub for distributing and concentrating data

trb_net16_hub_func

some functions used in hub_base

Application interface

trb_net16_api_base

The base application interface. It can act in two ways: As an active api, that can send data on its own and as a passive api that sends data only as reply on an incoming transfer

trb_net16_api_active
trb_net_api_passive

A active resp. passive application interface. This is only a wrapper for trb_net_base_api, connecting the right channels together

trb_net16_term

A simplified application interface. It only indicates if an trigger has been received and allows the application to set the errorbits and the time when den channel should be released.

"User convenience files"

trb_net16_endpoint_*

These are complete network entpoints with multiplexer, iobuf and api/trg interface. The number of trigger and application interfaces is given in the filename

trb_net16_regIO

A passive application to read and write registers over the network. Maybe some DMA-like access will be implemented later.