Structure

The main idea is to include additional debug information inside the data block (either send by TRBNet or on the classical way). This information should not go to the normal HADES event. It is only for hardware developers to check the data sources and consistency of the events during the set-up phase of the new DAQ system.

Therefore, these block can be hidden in the hld-data (sometimes also the DAQ-group needs external programs to analyze the debugging-headers). The proposal is to use a free bit in the sub-event-ID to switch the unpacker to a different mode taking the additional header into account. This header has the following syntax:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Len Vers det-ID trigger-tag TRBNet-Adress

Len
Length of the block including header and trailer (00 = 2, 01 = 4, 10 = 8, 11 = 16)
Vers
Version number (00)
det-ID
Detector ID
  • 0000 = not defined
  • 0001 = Start
  • 0010 = RICH
  • 0011 = MDC
  • 0100 = TOF
  • 0101 = RPC
  • 0110 = Shw
  • 0111 = FW
  • 1000 = Veto
  • 1001 = CTS (scalers, latches)
  • 1010 = ...

The last word of the debug block (trailer) is always the number of consecutive words of the data (with 0xffffffff = don't know). This means each unpacker can, independently from the content of the debug block:

  1. skip the debug block
  2. check the consistency of the length

Syntax length=2

This brings us to the syntax of the smallest block:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Len res. det-ID trigger-tag TRBNet-Adress
Data length

N.B. that the version bits can be re-used for different purposes

Syntax length=4

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Len 00 det-ID trigger-tag TRBNet-Adress
16-bit from the LVL1-TRM error pattern reserved
reserved
Data length

-- IngoFroehlich - 14 Aug 2008
Topic revision: r4 - 21 Aug 2008, MichaelTraxler
 
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